Heinz Jäckel

A 100-mW 4/spl times/10 Gb/s transceiver in 80-nm CMOS for high-density optical interconnects

This paper describes a quad optical transceiver for low-power high-density short-distance optical data communication. Each channel transmits 10 Gb/s over a multimode (MM) fiber and features a link margin of 5.2 dB at a bit error rate (BER) of 10/sup -12/. The transmit and receive amplifying circuits are implemented in an 80-nm digital CMOS process. Each driver consumes 2 mW from a 0.8-V supply, and each vertical cavity surface-emitting laser (VCSEL) requires 7 mA from a 2.4-V supply. The receiver excluding the output buffer consumes 6 mW from a 1.1-V supply per channel and achieves a transimpedance gain of 80.1 dB/spl Omega/. The isolation to the neighboring channels is >30dB including the bond wires and optical components. A detailed link budget analysis takes the relevant system impairments as losses and power penalties into account, derives the specifications for the electrical circuits, and accurately predicts the link performance. This work presents the highest serial data rate for CMOS transceiver arrays and the lowest power consumption per data rate reported to date.

Varactor-loaded transmission-line phase shifter at C-band using lumped elements

The design of varactor-loaded transmission-line phase shifters using lumped elements is discussed in this paper. A monolithic-microwave integrated-circuit (MMIC) phase shifter is fabricated to verify the proposed topology. Only one control voltage is required for phase control. Within a continuously adjustable phase-control range of 360/spl deg/ and a frequency range from 5 to 6 GHz, a low transmission loss of 4 dB/spl plusmn/1.7 dB is measured. The phase shifter is realized with a commercial 0.6-/spl mu/m GaAs MESFET process and requires a chip area of only 0.8 mm/sup 2/. To the knowledge of the authors, the best results reported to date are reached for a continuously adjustable passive phase shifter with comparable circuit size. The presented circuit is well suited to wireless adaptive antenna transceivers, operating in accordance with the 802.11a, high-performance radio local-area-network and high-speed wireless-access-network type-a standard.

Quantum Cascade Detectors

This paper gives an overview on the design, fabrication, and characterization of quantum cascade detectors. They are tailorable infrared photodetectors based on intersubband transitions in semiconductor quantum wells that do not require an external bias voltage due to their asymmetric conduction band profile. They thus profit from favorable noise behavior, reduced thermal load, and simpler readout circuits. This was demonstrated at wavelengths from the near infrared at 2 mum to THz radiation at 87 mum using different semiconductor material systems.

A low-power 20-GHz 52-dB/spl Omega/ transimpedance amplifier in 80-nm CMOS

This paper describes the design of a transimpedance amplifier (TIA) for a low-power, short-distance, high-density fiber-optic interconnect communication system. The single-ended circuit has been designed in an 80-nm digital CMOS process and consumes only 2.2 mW from a 1-V supply. The measured results show a transimpedance gain of 52 dB/spl Omega/ and a large bandwidth of 20 GHz. This work presents the highest bandwidth at the lowest power consumption for CMOS transimpedance amplifiers reported to date.

A low supply voltage SiGe LNA for ultra-wideband frontends

A low-power low-noise amplifier (LNA) for ultra-wideband (UWB) radio systems is presented. The microwave monolithic integrated circuit (MMIC) has been fabricated using a commercial 0.25-/spl mu/m silicon-germanium (SiGe) bipolar CMOS (BiCMOS) technology. The amplifier uses peaking and feedback techniques to optimize its gain, bandwidth and impedance matching. It operates from 3.4 to 6.9GHz, which corresponds with the low end of the available UWB radio spectrum. The LNA has a peak gain of 10dB and a noise figure less than 5dB over the entire bandwidth. The circuit consumes only 3.5mW using a 1-V supply voltage. A figure of merit (FoM) for LNAs considering bandwidth, gain, noise, power consumption, and technology is proposed. The realized LNA circuit is compared with other recently published low-power LNA designs and shows the highest reported FoM.

Low-power ultra-wideband wavelets generator with fast start-up circuit

A low-power fully integrated ultra-wideband (UWB) wavelet generator is presented. This UWB generator is intended for low-power and low-complexity UWB radio technology using the noncoherent energy collection approach. The wavelet generator is based on a cross-coupled inductance-capacitance (LC) oscillator. It can be directly driven by two digital signals, which can modulate the length, position, and phase of the output wavelet. An additional digital circuit improves the startup time of the oscillator so that the oscillator and output buffers can be switched off between each wavelet generation. The entire chip-including output buffers-uses a 0.18-/spl mu/m CMOS technology. When operating at 10 megapulses per second (Mp/s) with a 1.2-GHz bandwidth wavelet, the generator provides a typical average output power of -20 dBm and consumes only 1.8 mW. The differential output signal is a multicycle waveform centered at 4.5 GHz.

60 GHz VCO with wideband tuning range fabricated on VLSI SOI CMOS technology

A 60 GHz cross-coupled differential LC CMOS VCO is presented in this paper, which is optimized for a large frequency tuning range using conventional MOSFET varactors. The MMIC is fabricated on digital 90 nm SOI technology and requires a circuit area of less than 0.1 mm/sup 2/ including the 50 /spl Omega/ output buffers. Within a frequency control range from 52.3 GHz to 60.6 GHz, a supply voltage of 1.5 V and a supply current of 15 mA, the circuit dividers a very constant output power of -6.8 /spl plusmn/ 0.2 dBm and yields a phase noise between -85 to -92 dBc/Hz at 1 MHz frequency offset.

All-optical switching at multi-100-Gb/s data rates with Mach-Zehnder interferometer switches

We present experimental and theoretical results on ultrafast nonlinear dynamics in InGaAsP semiconductor optical amplifiers (SOAs). Carrier heating, spectral hole burning, and two-photon absorption are analyzed by heterodyne pump-probe experiments which deliver basic model parameters like gain-phase coupling parameters of the material. The impact on the device performance induced by these physical effects is verified by cross-gain/cross-phase experiments on InGaAsP-based SOAs and Mach-Zehnder interferometer switches. In the co-propagation arrangement, the switching window with maximum transmission is shown to be 1.5 ps which translates into demultiplexing capabilities beyond 600 Gb/s. Calculations based on a distributed rate equation model show that, for high-speed applications, the switching window can be limited by pulse saturation and by subpicosecond nonlinear effects.

A 25-Gb/s CDR in 90-nm CMOS for High-Density Interconnects

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of <10-12 and tracks frequency deviations between the incoming data and the reference clock of up to plusmn122 ppm. The sinusoidal jitter tolerance is >0.35UIpp for jitter frequencies les100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UIpp at a BER=10-12. The core CDR circuit occupies a chip area of 0.07 mm2 and consumes 98 mW from a 1.1-V supply

30-40-GHz drain-pumped passive-mixer MMIC fabricated on VLSI SOI CMOS technology

In this paper, a passive down mixer is proposed, which is well suited for short-channel field-effect transistor technologies. The authors believe that this is the first drain-pumped transconductance mixer that requires no dc supply power. The monolithic microwave integrated circuit (MMIC) is fabricated using digital 90-nm silicon-on-insulator CMOS technology. All impedance matching, bias, and filter elements are implemented on the chip, which has a compact size of 0.5 mm/spl times/0.47 mm. The circuit covers a radio frequency range from 30 to 40 GHz. At a RF frequency of 35 GHz, an intermediate frequency of 2.5 GHz and a local-oscillator (LO) power of 7.5 dBm, a conversion loss of 4.6 dB, a single-sideband (SSB) noise figure (NF) of 7.9 dB, an 1-dB input compression point of -6 dBm, and a third-order intercept point at the input of 2 dBm were measured. At lower LO power of 0 dBm, a conversion loss of 6.3 dBm and an SSB NF of 9.7 dB were measured, making the mixer an excellent candidate for low power-consuming wireless local-area networks. All results include the pad parasitics. To the knowledge of the authors, this is the first CMOS mixer operating at millimeter-wave frequencies. The achieved conversion loss is even lower than for passive MMIC mixers using leading edge III/V technologies, showing the excellent suitability of digital CMOS technology for analog circuits at millimeter-wave frequencies.