Christian Lindholm

An Optimized Driver for SiC JFET-Based Switches Enabling Converter Operation With More Than 99% Efficiency

This paper presents the single channel galvanically isolated gate driver optimized for driving a normally-on silicon carbide junction field effect transistor (SiC JFET) also presented at ISSCC 2012 [1]. The idea of the chosen direct drive JFET concept is to switch power with a normally-on SiC JFET, using the high voltage breakdown capability of the SiC JFET and ensuring a safe normally-off behavior using a normally-off low voltage MOSFET in series. By controlling the transistor gates individually the JFET can be driven with minimum switching losses and good control. The driver makes the operation and handling of normally-on SiC JFETs as safe as normally-off switches, thereby simplifying the integration of normally-on SiC JFETs into systems like switch mode power supplies. To transfer the signal from the controller to the driver over a needed galvanic isolation of 1700 V a two chip solution with a coreless transformer arranged in one package was chosen, using a 0.6 μm BiCMOS and a 0.8 μm BCD technology. Powering of the gate driver through bootstrapping has been made possible, due to the direct drive JFET concept and the further integration of supervision and control circuitry and a negative voltage regulator that regulates the entire p-substrate of the driver chip. Tested together with the JFET in a buck converter efficiencies over 99% have been measured.

Switched capacitor DC-DC converter in 65nm CMOS technology with a peak efficiency of 97%

This paper presents a highly efficient switched capacitor (SC) DC-DC converter, which is implemented in a 65nm low power CMOS process to enable SoC integration. The converter supplies a nominal output current of 30mA with an efficiency of 95%. The buck converter operates with a constant input voltage of 1.83V and produces an output voltage of 1.2V. The charge is transported in two phases from the input supply to the output capacitor. Therefore, a network consisting of switches and two so-called flying capacitors are used. This converter is intended to be used in power management units for mobile devices and to substitute complex and expensive inductor based DC-DC converters. A test chip was designed in collaboration with Infineon Technologies Austria AG. The measurement results are presented and give for an output current of 10mA a peak efficiency of 97%.

An optimized driver for SiC JFET-based switches delivering more than 99% efficiency

Nowadays, there is a high demand for highly efficient power converters that can be put in systems such as power factor correctors or solar panels. A silicon carbide (SiC) based power switch has a very good performance when it comes to switching and conduction losses. As on silicon, the manufacturing of junction devices is easier than MOSFET devices because the growth of highly reliable oxide is very challenging [1]. Recently, a family of high-voltage SiC junction FET (JFET) transistors has been developed which has made it possible to reach an efficiency of more than 99% with a buck converter. The low switching loss of these transistors allows for the use of a higher switching frequency and smaller external components which in turn reduce PCB area and overall system cost. A dedicated gate driver with possible bootstrap operation has been developed for a normally-on n-type JFET. It allows maximum efficiency, operation as safe as that of a normally-off switch, and reduced number of external components because of integration of voltage regulator and supervision circuitry. Bootstrapping minimizes the number of supplies needed for the power converter and reduces board space and BOM.

High frequency and low power semi-synchronous PFM state machine

The finite state machine (FSM) needed for the low power system pulse frequency modulated (PFM) mode in a buck converter is usually asynchronous because the fast clock needed for a synchronous FSM consumes too much power, or is maybe even not available. However, the implementation, verification and testing of a asynchronous FSM is complicated compared to an synchronous one. This paper presents a concept of a semi-synchronous FSM that combines the benefits of both synchronous and asynchronous state machines. The result is a FSM which runs at high clock frequency, consumes very little power and can be implemented, verified and tested as a synchronous FSM. This concept has been used to design a PFM FSM in a field programmable gate array (FPGA) and in a 65 nm CMOS technology.

Smart power: From problem statement to system solution

This paper demonstrates the design of a high power, high efficiency inverter based on SiC (Silicon Carbide) JFET (Junction Field Effect Transistor) switches. It starts with a problem statement, i.e. which requirements are to be fulfilled, discusses design solutions, and ends with some measurements of the complete system. The final design is able to handle more than 1000V, currents of more than 30A and achieves a peak efficiency of more than 99% in a buck configuration [1].