Dieter Draxelmayr

A 6b 600MHz 10mW ADC array in digital 90nm CMOS

A 6b converter array operates at a 600MHz clock frequency with input signals up to 600MHz and only 10mW power consumption. The array consists of 8 interleaved successive approximation converters implemented in a 90nm digital CMOS technology.

A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB

A fully integrated WiMedia/MBOA-compliant RF transceiver for UWB data communication in the 3 to 5GHz band is presented. It is designed in a 0.13mum standard CMOS process with 1.5V single supply voltage. The NF is between 3.6 and 4.1dB over all 3 bands. On the TX side, the P1dB is 5dBm supporting an EVM of -28dB and up to -4dBm output power. A single-PLL LO generation is included

Spectral shaping of timing mismatches in time-interleaved analog-to-digital converters

We introduce spectral shaping of timing mismatches in time-interleaved analog-to-digital converters (TIADCs). We show how to reorder the channel ADC sequence in order to achieve spectral shaping and provide optimization criteria. We present a simple channel sorting algorithm, which significantly improves the signal-to-noise and distortion ratio (SINAD) and the spurious free dynamic range (SFDR) by applying a simple low-pass filter. The power consumption of the presented timing mismatch compensation method is very low compared to other methods and does not significantly scale with the number of channel ADCs. Furthermore, the compensation method does not depend on the absolute accuracy of the identified timing mismatches, which vastly relaxes the requirements on timing mismatch identification methods.

An Optimized Driver for SiC JFET-Based Switches Enabling Converter Operation With More Than 99% Efficiency

This paper presents the single channel galvanically isolated gate driver optimized for driving a normally-on silicon carbide junction field effect transistor (SiC JFET) also presented at ISSCC 2012 [1]. The idea of the chosen direct drive JFET concept is to switch power with a normally-on SiC JFET, using the high voltage breakdown capability of the SiC JFET and ensuring a safe normally-off behavior using a normally-off low voltage MOSFET in series. By controlling the transistor gates individually the JFET can be driven with minimum switching losses and good control. The driver makes the operation and handling of normally-on SiC JFETs as safe as normally-off switches, thereby simplifying the integration of normally-on SiC JFETs into systems like switch mode power supplies. To transfer the signal from the controller to the driver over a needed galvanic isolation of 1700 V a two chip solution with a coreless transformer arranged in one package was chosen, using a 0.6 μm BiCMOS and a 0.8 μm BCD technology. Powering of the gate driver through bootstrapping has been made possible, due to the direct drive JFET concept and the further integration of supervision and control circuitry and a negative voltage regulator that regulates the entire p-substrate of the driver chip. Tested together with the JFET in a buck converter efficiencies over 99% have been measured.

An optimized driver for SiC JFET-based switches delivering more than 99% efficiency

Nowadays, there is a high demand for highly efficient power converters that can be put in systems such as power factor correctors or solar panels. A silicon carbide (SiC) based power switch has a very good performance when it comes to switching and conduction losses. As on silicon, the manufacturing of junction devices is easier than MOSFET devices because the growth of highly reliable oxide is very challenging [1]. Recently, a family of high-voltage SiC junction FET (JFET) transistors has been developed which has made it possible to reach an efficiency of more than 99% with a buck converter. The low switching loss of these transistors allows for the use of a higher switching frequency and smaller external components which in turn reduce PCB area and overall system cost. A dedicated gate driver with possible bootstrap operation has been developed for a normally-on n-type JFET. It allows maximum efficiency, operation as safe as that of a normally-off switch, and reduced number of external components because of integration of voltage regulator and supervision circuitry. Bootstrapping minimizes the number of supplies needed for the power converter and reduces board space and BOM.

A

−This paper presents an integrated current-sensing system (CSS) that is intended for use in battery-powered devices. It consists of a 10-mΩ on-chip metal shunt resistor, a switchedcapacitor ΔΣ ADC, and a dynamic bandgap reference (BGR) that provides the ADC’s reference voltage and also senses the shunt’s temperature. The CSS is realized in a standard 0.13-μm CMOS process, occupies 1.15 mm and draws 55 μA from a 1.5-V supply. Extensive measurements were made on 24 devices, 12 of which were directly bonded to a printed-circuitboard (PCB) and 12 of which were packaged in a standard HVQFN plastic package. For currents ranging from –5 A to +5 A and over a temperature range of –55°C to +85°C, they exhibit a maximum offset of 16 μA and a maximum gain error of ±0.3%. This level of accuracy represents a significant improvement on the state-of-the-art, and was achieved by the use of an accurate shunt temperature compensation scheme, a low-leakage sampling scheme and several dynamic error correction techniques. Index Terms−Coulomb counter, current-sensing system, metal shunt resistor, dynamic bandgap reference, temperature sensor, temperature compensation. This is the authors version of an article that has been published in this journal. Changes were made to this version by the publisher prior to publication. The final version of record is available at http://dx.doi.org/10.1109/JSSC.2015.2511168 (c) 2018 European Union Copyright. Personal use is permitted. For any other purposes, permission must be obtained from the IEEE by emailing pubs-permissions@ieee.org.

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This paper presents a micropower current-sensing system (CSS) for battery monitoring, which consists of a calibrated shunt resistor, a ΔΣ ADC, and a dynamic bandgap reference (BGR). For currents ranging from 0 to 1A over the industrial temperature range (-40°C to +85°C), it exhibits 10μA offset and ±0.03% (3σ) gain error, which is a 3× improvement on systems with off-chip external references [1,2]. This level of accuracy is achieved by the use of dynamic error-correction techniques, digital temperature compensation, and an on-chip dynamic BGR, whose spread is corrected by a single room-temperature trim.

A Integrated Current-Sensing System With

Low-k dielectrics will be required to continue miniaturisation of integrated circuits beyond the 90 nm node. The integration of these advanced materials results in significant reduction of signal delay and power dissipation compared to conventional silicon dioxide. As the technology continues to advance, the implementation of low-k dielectrics for the 65 nm node (Luo, et al., 2004) causes also problems, when using backend of line (BEOL) capacitors in mixed signal circuits. Especially the dielectric absorption effect increases dramatically. It limits the performance of capacitors and the circuits, where the capacitors are used (Zanchi, et al., 2000). A SAR ADC is a good example to show the impact of this effect. This paper presents the extraction and the modelling of the dielectric absorption effect of a low-k material as well as its influence on the resolution of a differential 16 bit SAR ADC

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This paper presents an integrated shunt-based current-sensing system (CSS) capable of handling ±36A currents, the highest ever reported. It also achieves 0.3% gain error and 400μA offset, which is significantly better than the state-of-the-art. The heart of the system is a robust 260μΩ shunt made from the lead-frame of a standard HVQFN plastic package. The resulting voltage drop is then digitized by a ΔΣ ADC and a bandgap reference (BGR). At the expense of current handling capability, a ±5A version of the CSS uses a 10mΩ on-chip metal shunt to achieve just 4μA offset. Both designs were realized in a standard 0.13μm CMOS process.

% Gain Error and 16 μA Offset From

This paper presents a fully integrated current-sensing system (CSS) that is 10x more accurate than the state-of-the-art. It consists of an on-chip shunt resistor, a ΔΣ ADC and a bandgap reference (BGR), which also senses shunt temperature. For ±5A currents, it exhibits 12μA offset and ±0.25% gain error from -40 to +85°C. This level of accuracy is achieved with the help of multiple dynamic error correction techniques, a shunt temperature compensation scheme and chip-scale packaging for low thermal and electrical resistance.