Christian Marot

Control of the electromagnetic compatibility: An issue for IC reliability

Abstract This paper deals with the use of two main standard modeling approaches in order to control the electromagnetic compatibility of an IC before manufacturing. An application is given in the case of a complex mixed circuit which is an Analog to Digital Converter (ADC) embedded in a microcontroller. The digital core (DC) of the microcontroller consumes dynamic currents which generate internal disturbances and, as a consequence, a loss of the ADC accuracy is observed. At first, the conducted emission of the DC is estimated by using the ICEM-CE model. Then, the ADC immunity is modeled with ICIM-CI methodology. Based on these two models, a simulation at the chip level is performed to estimate the loss of accuracy of this ADC. Finally, this study is the first step in the development of a methodology for virtual prototyping allowing, from the design, the evaluation of the integrated circuit sensitivity to electromagnetic interference in order to improve its reliability.

EMC standards at IC level - status of IEC and technical goals of the SEISME project

This paper reviews the methods proposed by the International Electrotechnical Commission (IEC) for characterizing and modelling of Electromagnetic Compatibility (EMC) of Integrated Circuits (IC). The development of tools and EMC performance prediction methods is also described in the context of IC obsolescence, through the French research project SEISME.

Modeling Methodology of Automotive Electronic Equipment Assessed on a Realistic Subsystem

Conducted disturbances induced into automotive electronic equipment can be predicted in the early design phase by numerical simulation. This supposes a realistic modeling of the cable harness, as well as the electronic equipment. This paper evaluates a modeling method by the results obtained on a realistic automotive subsystem. The latter is composed of two pieces of electronic equipment connected to each other by a cable harness. This test case was performed on printed circuit boards (PCBs) with full or partial ground planes and using a representative sample of harnesses. Simulation results are compared with measurement results using multiple cable harness samples. A good agreement between measurement and simulation can be obtained for PCBs with full ground plane, provided that fringing effects of the electronic components are taken into account in the equipment model.

Construction of an Integrated Circuit Emission Model of a FPGA

This paper describes the construction flow and the validation of an equivalent conducted emission model of a complex integrated circuit (a FPGA), based on the ICEM (Integrated Circuit Emission Model) modeling approach.

Near-field scan - State of the art and standardisation

Near-field scan techniques have considerably evolved over recent years and will no doubt continue to do so in the future. Standardisation of these measurement techniques ensures stable reproducibility and provides guideline for those who are new to the field. The state of the art is summarised and the evolution of applicable standards is described.

Spread spectrum clocking applied to charge pump for conducted emission improvement in automotive

The aim of this paper is, first of all, to make a status about the Conducted Emission (CE) level of devices integrating a charge pump, currently used in automotive Electronic Control Unit (ECU). Then, the spread spectrum clocking method, in order to reduce CE levels, applied to such device is studied and results are presented.

Immunity modelling of electronics board

Electronic boards will become higher density of integration with lower supply voltages. Internal integrated Circuits have more and more gates on silicon and Printed circuits Boards use many high density technologies. That size reduction integration with nearby signals positions promotes internal crosstalk, sizes reduction of die geometries increases unwanted current in parasitic structure as isolation capacitances. Consequently, the immunity of electronic boards is becoming more and more critical and the use of models and simulation tools is hardly required to optimize during the design phases the susceptibility behaviour and also to predict the immunity strength to conducted disturbances both at the IC and the application level. This paper introduces in section I an overview of the IEC projects for Integrated Circuit modelling. An immunity model for an electronic board is described in section II. Example model of driver bus is presented in a part III. Simulation results of a immunity test with that driver immunity model is presented in a part IV.

Near field measurement for EMC validation of electronics board in IMA

Today the electronic embedded architecture in aircraft is based on traditional approaches on the independent aircraft systems with modules called LRU, Line Replaceable Unit. Needs to reduce cost and weight of the embedded electronic units pass by the implementation of a more modular electronics in the architectures AC with elementary module. Such EMC avionic tests description at electronics modules levels are not defined today. The objectives of those studies are to give technical data to defined EMC test setup and associated limits at modules levels to respect environment requirements.