Sonia Ben Dhia

On-Chip Noise Sensor for Integrated Circuit Susceptibility Investigations

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of noncompliance becomes critical for circuit designers. However, an on-chip characterization of noise is still necessary for model validation and design optimization. Although different on-chip measurement solutions have been proposed for emission issue characterization, no on-chip measurement methods have been proposed to address the susceptibility issues. This paper presents an on-chip noise sensor dedicated to the study of circuit susceptibility to electromagnetic interferences. A demonstration of the sensor measurement performances and benefits is proposed through a study of the susceptibility of a digital core to conducted interferences. Sensor measurements ensure a better characterization of actual coupling of interferences within the circuit and a diagnosis of failure origins.

Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied Science (INSA), Toulouse, France. Collaborations among the faculty members of the two institutions have produced a set of learning resources and design tools to support the development of industry-relevant design skills and lifelong learning skills. At the pedagogical level, the emphasis is on the development of practical circuit design, critical thinking, and problem-solving skills rather than the mastery of complex circuit design tools. The courses enable students to learn about the most recent technological developments and their implications, using a set of user-friendly tools. The PBL methodologies, intuitive design tools, and latest technology models have consistently produced high levels of student satisfaction with the overall quality of the courses at the two institutions.

Modeling and Simulation of LDO Voltage Regulator Susceptibility to Conducted EMI

This paper presents a methodology dedicated to modeling and simulation of low-dropout (LDO) voltage regulator susceptibility to conducted electromagnetic interference (EMI). A test chip with a simple LDO structure was designed for EMC test and analysis. A transistor-level model, validated by functional tests, Z-parameter characterization and direct power injection (DPI) measurements, is used to predict the immunity of the LDO regulator. Different levels of model extraction reveal the weight contributions of subcircuits and parasitic elements on immunity issues. The DPI measurement results show a good fit with model prediction up to 1 GHz.

Characterization of Changes in LDO Susceptibility After Electrical Stress

The low dropout voltage regulator (LDO) is very sensitive to electromagnetic interference (EMI) coupled onto the power supply, with concomitant output voltage offset. Most electromagnetic compatibility analyses of the LDO do not account for the effects of ageing. However, device ageing can degrade the physical parameters of semiconductor devices and can worsen the effect of EMI. This paper analyses the drift in LDO immunity after accelerated ageing. A large number of measurements that show the variations in the test results for dc characteristic, impedance, and immunity reveal increasing susceptibility after electrical accelerated ageing.

Long-term Electro-Magnetic Robustness of Integrated Circuits: EMRIC research project

This paper presents the scientific achievements of EMRIC project that aimed at developing a new research activity which mixes EMC and IC reliability. This project contributes to improve the electromagnetic robustness (EMR) of integrated circuits over the full life-time of the electronic system, with a special emphasis on deep submicron technology. The results of this project give a unique overview about EMR in the scientific community and will contribute to develop EMR qualification procedures, EMR design techniques and EMR predictive methods.

Experimental Investigations into the Effects of Electrical Stress on Electromagnetic Emission from Integrated Circuits

Recent studies have shown that the aging of integrated circuits may modify electromagnetic emission significantly. This paper reports on an experiment to elucidate the origins of emission level changes in a test chip using 90-nm CMOS technology. Circuit analysis, combined with electromagnetic emission and on-chip power supply voltage bounce measurements made during the application of electric stress, have identified the role of intrinsic wear-out mechanisms, which contribute to a progressive change in the transient current produced by the circuit.

Effect of Aging on Power Integrity and Conducted Emission of Digital Integrated Circuits

Recent studies have shown that integrated circuit aging modifies electromagnetic emission significantly. The proposed paper aims at evaluating the impact of aging on the power integrity and the conducted emission of digital integrated circuits, clarifying the origin of electromagnetic emission evolution and proposing a methodology to predict this evolution. On-chip measurements of power supply voltage bounces in a CMOS 90 nm technology test chip and conducted emission measurements are combined with electric stress to characterize the influence of aging. Simulations based on ICEM modeling modified by an empirical coefficient to model the evolution of the emission induced by device aging is proposed and tested.

Ageing effect on immunity of a mixed signal IC

This paper presents an original study aiming at evaluating the drift of susceptibility level of a mixed signal circuit. The paper first addresses the measurement set-ups and the recommendations required to extract susceptibility level variations. Then experimental results are presented and show that the immunity of some blocks of the circuit under test can be significantly reduced after a standard aging procedure.

Near-field scan - State of the art and standardisation

Near-field scan techniques have considerably evolved over recent years and will no doubt continue to do so in the future. Standardisation of these measurement techniques ensures stable reproducibility and provides guideline for those who are new to the field. The state of the art is summarised and the evolution of applicable standards is described.

Design of on-chip sensors to monitor electromagnetic activity in ICs: Towards on-line diagnosis and self-healing

With the growing concerns about electromagnetic compatibility of integrated circuits, the need for accurate prediction tools and models to reduce risks of non-compliance becomes critical for circuit designers. On-chip characterization of noise becomes necessary for model validation and design optimization to reduce redesign costs and time-to-market for IC manufacturers. This paper presents an on-chip noise sensor dedicated to the study of various aspects of electromagnetic compatibility at circuit level, such as power and signal integrity, substrate coupling, conducted emission and susceptibility to electromagnetic interferences. The different architectures of the sensor are presented as well as a demonstration of its measurement performance and benefits through many case studies. Applications of on-chip measurement may be extended towards online diagnosis and self-healing.