Christian Philipp Sandow

Analysis of the latch-up process and current filamentation in high-voltage trench-IGBT cell arrays

We present a theoretical analysis of the formation of current filaments leading to the latch-up state that can occur during the turn-off process in a cell array of high-voltage (3.3 kV) trench insulated-gate bipolar transistors (trench IGBTs). Our investigations, based on self-consistent physical device simulations, aim at understanding the behavior of multiple cells, i.e. parallel cells as well as integrated structures, during overcurrent turnoff by studying the behavior of a representative single cell under identical conditions. With these insights we are able to analyse the latch-up mechanism itself as well as its consequences for the robustness of the device against latch-up. Furthermore, we gain an understanding of the formation of current filaments inside IGBT cells and their relation to device latch-up.

Evolution of current filaments limiting the safe-operating area of high-voltage trench-IGBTs

An improved understanding of the physical processes leading to the formation of current filaments and latch-up in large arrays of monolithically integrated high voltage (3.3kV) trench-IGBT cells during the turn-off process of the device is the prerequisite for enhancing the robustness of the device. To this end, numerical simulations have been performed revealing the rim of the safe-operating area (SOA) and what happens beyond it.

Exploring the limits of the safe operation area of power semiconductor devices

TCAD simulations of power devices are an important tool to investigate destruction mechanisms of power diodes and IGBTs. It is found that the dynamics of filamentation is the key for understanding the limits of the safe operation area. For both diodes and IGBTs, destructive and non-destructive filamentation mechanisms are identified and the resulting destruction mechanisms are discussed.

Predictive half-cell simulations of filament formation during IGBT turn-off

We present experimental data and simulation methods concerning the destruction of Insulated Gate Bipolar Transistors (IGBTs) during inductive turn-off when dynamic avalanche occurs. The influence of cell pitch and gate resistor on destruction is explored and the occurrence of current fllamentation is proposed to be a necessary condition for destruction. In order to validate this hypothesis, transient isothermal two-dimensional (2D) multi-cell simulations are performed. The simulation results reproduce the experimental results very well and reveal that the most critical conditions for fllamentation occur at that gate resistor value at which the discussed IGBT exhibits strongest avalanche generation. To replace the time demanding multi-cell simulations, an alternative simulation approach based on the occurrence of negative differential resistance in half-cell output characteristics is proposed and verified.

Free-carrier absorption experiments for the investigation of the physical device properties in IGBTs with hydrogen-related donors

Hydrogen-related donors can be advantageously used in IGBTs and power diodes with a view to creating field-stop layers and to optimising the electrical performance. In this work, the influence of hydrogen-related donors on the on-state plasma profile in field-stop IGBTs is analysed by means of free-carrier absorption measurements. For these investigations, dedicated IGBT test structures were used, which had been adapted to the specific properties of the employed measurement set-up. Two different hydrogen-related donor profiles were implanted into these IGBT samples and, subsequently, measurements with different current densities were compared to 2D TCAD numerical simulations. In the next step, the simulation models were adjusted, with respect to carrier lifetime and mobility to reflect the impact of a possible variation of these properties.

Influence of quasi-3D filament geometry on the latch-up threshold of high-voltage trench-IGBTs

Current filaments are inherently three-dimensional phenomena regardless of the chip topography, which can be stripe-or checkerboard-shaped. Therefore, we consider an alter-native mapping of the real-chip IGBT cell topography to a quasi-3D simulation geometry in order to attain a computationally affordable approximation of 3D-filamentation effects that limit the SOA. The new approach extends that of previous work ([1], [2]) by using large, monolithically integrated cell arrays as simulation domain in cylindrical cell geometry (Figs. 1, 2), resulting in cylindrical filaments. In this way we obtain a quasi-3D and, hence, more realistic approximation of the filamentary current flow and the resulting critical phenomena in real-world IGBT-chips, which provides the basis for the quantitative numerical analysis of the latch-up threshold.