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Dive into the research topics where Frank Dieter Pfirsch is active.

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Featured researches published by Frank Dieter Pfirsch.


international conference on simulation of semiconductor processes and devices | 2013

Analysis of the latch-up process and current filamentation in high-voltage trench-IGBT cell arrays

C. Toechterle; Frank Dieter Pfirsch; Christian Philipp Sandow; G. Wachutka

We present a theoretical analysis of the formation of current filaments leading to the latch-up state that can occur during the turn-off process in a cell array of high-voltage (3.3 kV) trench insulated-gate bipolar transistors (trench IGBTs). Our investigations, based on self-consistent physical device simulations, aim at understanding the behavior of multiple cells, i.e. parallel cells as well as integrated structures, during overcurrent turnoff by studying the behavior of a representative single cell under identical conditions. With these insights we are able to analyse the latch-up mechanism itself as well as its consequences for the robustness of the device against latch-up. Furthermore, we gain an understanding of the formation of current filaments inside IGBT cells and their relation to device latch-up.


international symposium on power semiconductor devices and ic's | 2014

Evolution of current filaments limiting the safe-operating area of high-voltage trench-IGBTs

C. Toechterle; Frank Dieter Pfirsch; Christian Philipp Sandow; Gerhard Wachutka

An improved understanding of the physical processes leading to the formation of current filaments and latch-up in large arrays of monolithically integrated high voltage (3.3kV) trench-IGBT cells during the turn-off process of the device is the prerequisite for enhancing the robustness of the device. To this end, numerical simulations have been performed revealing the rim of the safe-operating area (SOA) and what happens beyond it.


Archive | 2007

Study of Time-Periodic Avalanche Breakdown Occurring in VLD Edge Termination Structures

U. Knipper; Frank Dieter Pfirsch; Thomas Raker; J. Niedermeyr; G. Wachutka

IGBT device destruction often occurs localized at the edge termination. Among various termination techniques, “variation of lateral doping” (VLD) is a promising candidate to increase the ruggedness of IGBT chips. We analyzed the time-dependent behavior of VLD edge termination during avalanche breakdown by numerical simulations demonstrating the advantage of this technique. Measurements on IGBT test devices with VLD edge termination are in agreement with the simulations.


international conference on simulation of semiconductor processes and devices | 2014

Exploring the limits of the safe operation area of power semiconductor devices

Christian Philipp Sandow; Roman Baburske; Franz Josef Niedernostheide; Frank Dieter Pfirsch; C. Töchterle

TCAD simulations of power devices are an important tool to investigate destruction mechanisms of power diodes and IGBTs. It is found that the dynamics of filamentation is the key for understanding the limits of the safe operation area. For both diodes and IGBTs, destructive and non-destructive filamentation mechanisms are identified and the resulting destruction mechanisms are discussed.


international conference on simulation of semiconductor processes and devices | 2016

Influence of quasi-3D filament geometry on the latch-up threshold of high-voltage trench-IGBTs

C. Toechterle; Frank Dieter Pfirsch; Christian Philipp Sandow; Gerhard Wachutka

Current filaments are inherently three-dimensional phenomena regardless of the chip topography, which can be stripe-or checkerboard-shaped. Therefore, we consider an alter-native mapping of the real-chip IGBT cell topography to a quasi-3D simulation geometry in order to attain a computationally affordable approximation of 3D-filamentation effects that limit the SOA. The new approach extends that of previous work ([1], [2]) by using large, monolithically integrated cell arrays as simulation domain in cylindrical cell geometry (Figs. 1, 2), resulting in cylindrical filaments. In this way we obtain a quasi-3D and, hence, more realistic approximation of the filamentary current flow and the resulting critical phenomena in real-world IGBT-chips, which provides the basis for the quantitative numerical analysis of the latch-up threshold.


international symposium on power semiconductor devices and ic's | 2015

Critical overcurrent turn-off close to IGBT current saturation

Alexander Philippou; Christian Jaeger; Johannes Georg Laven; Roman Baburske; H.-J. Schulze; Frank Dieter Pfirsch; Franz Josef Niedernostheide; Antonio Vellei; H. Itani

A failure mechanism in the edge termination of a 1200V IGBT during overcurrent turn-off is studied with simulations and verified by experiments. The position of the destruction in the experiment can be correlated to the formation of a critical filament in the simulation. The destruction mechanism is investigated in detail. It is only observed if the IGBT enters its current saturation regime. I.e., the IGBT survives a turn-off from the same current level for an increased gate voltage. It is shown that an IGBT provided with a properly-designed High Dynamic Ruggedness (HDR) edge termination structure [1] is no longer susceptible to the destruction mechanism.


Archive | 2006

Semiconductor component with a low on-state resistance

Frank Dieter Pfirsch; Armin Willmeroth; Anton Mauder; Stefan Sedlmaier


Archive | 2012

Reverse Conducting IGBT

Frank Dieter Pfirsch; Dorothea Werber


Archive | 2013

Circuit with a plurality of bipolar transistors and method for controlling such a circuit

Franz Hirler; Anton Mauder; Frank Dieter Pfirsch


Archive | 2009

Semiconductor device and method for producing a semiconductor device

Franz Hirler; Frank Dieter Pfirsch

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