Christian Venerus

A TDC-Free Mostly-Digital FDC-PLL Frequency Synthesizer With a 2.8–3.5 GHz DCO

This paper presents the first published fully-integrated digital fractional- N PLL based on a second-order frequency-to-digital converter (FDC) instead of a time-to-digital converter (TDC). The PLLs quantization noise is nearly identical to that of a conventional analog delta-sigma modulator based PLL (ΔΣ-PLL). Hence, the quantization noise is highpass shaped and is suppressed by the PLLs loop filter to the point where it is not a dominant contributor to the PLLs output phase noise. However, in contrast to a ΔΣ-PLL, the new PLL has an entirely digital loop filter and its analog components are relatively insensitive to non-ideal analog circuit behavior. Therefore, it offers the performance benefits of a ΔΣ-PLL and the area and scalability benefits of a TDC-based digital PLL. Additionally, the PLLs digitally controlled oscillator (DCO) incorporates a new switched-capacitor frequency control element that is insensitive to supply noise and parasitic coupling. The PLL is implemented in 65 nm CMOS technology, has an active area of 0.56 mm2, dissipates 21 mW from 1.0 and 1.2 V supplies, and its measured phase noise at 3.5 GHz is -123, -135, and -150 dBc/Hz at offsets of 1, 3, and 20 MHz, respectively. The PLLs power consumption is lower than previously published digital PLLs with comparable phase noise performance.

Delta-Sigma FDC Based Fractional-N PLLs

Fractional-N phase-locked loop frequency synthesizers based on time-to-digital converters (TDC-PLLs) have been proposed to reduce the area and linearity requirements of conventional PLLs based on delta-sigma modulation and charge pumps (ΔΣ-PLLs). Although TDC-PLLs with good performance have been demonstrated, TDC quantization noise has so far kept their phase noise and spurious tone performance below that of the best comparable ΔΣ-PLLs. An alternative approach is to use a delta-sigma frequency-to-digital converter (ΔΣ FDC) in place of a TDC to retain the benefits of TDC-PLLs and ΔΣ-PLLs. This paper proposes a practical ΔΣ FDC based PLL in which the quantization noise is equivalent to that of a ΔΣ-PLL. It presents a linearized model of the PLL, design criteria to avoid spurious tones in the ΔΣFDC quantization noise, and a design methodology for choosing the loop parameters in terms of standard PLL target specifications.

A Class of Quantizers With DC-Free Quantization Noise and Optimal Immunity to Nonlinearity-Induced Spurious Tones

Fractional- N phase-locked loops (PLLs) typically use noise-shaping coarse quantizers to control their instantaneous output frequency. The resulting quantization noise and its running sum inevitably get distorted by non-ideal analog components within the PLL, which induces undesirable spurious tones in the PLLs output signal. A recently proposed quantizer, called a successive requantizer, has been shown to mitigate this problem. Its quantization noise and the running sum of its quantization noise can be subjected to up to fifth-order and third-order nonlinear distortion, respectively, without inducing spurious tones. This paper extends the previously published successive requantizer results to enable the design of successive requantizers whose quantization noise running sum sequences attain such immunity to nonlinearity-induced spurious tones up to arbitrarily high orders of distortion. The extended results are used to design example successive requantizers whose quantization noise and quantization noise running sum sequences have optimally reduced susceptibility to nonlinearity-induced spurious tones.

Simplified Logic for Tree-Structure Segmented DEM Encoders

Segmented dynamic element matching (DEM) encoders can be used in high-resolution digital-to-analog converters (DACs) to reduce nonlinear distortion that would otherwise arise from component mismatches while avoiding the high circuit complexity of non-segmented DEM encoders. This paper presents tree-structure segmented DEM encoders that have several advantages over prior segmented DEM encoders: they do not require digital adders, they have latencies that are linear rather than parabolic functions of the number of bits of DAC resolution, and they have lower hardware complexity than previously published architectures.

Quantization Noise Cancellation for FDC-Based Fractional-

This paper presents a quantization noise cancellation technique for frequency-to-digital converter-based fractional-N phase-locked loops (FDC-PLLs). The technique cancels quantization noise prior to the loop filter so the PLL bandwidth can be increased without a significant phase noise penalty. The paper also presents an FDC-PLL architecture enhancement that achieves the effect of a charge pump offset current to improve linearity without the extra current source required by previous implementations.

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Presents corrections to the article, “A TDC-free mostly-digital FDC-PLL frequency synthesizer with a 2.8–3.5 GHz DCO,” (Venerus, C. and Galton, I.) IEEE J. Solid-State Circuits, vol. 50, no. 2, pp. 450–463, Feb. 2015.