Christoforos E. Economakos

FPGA implementation of PLC programs using automated high-level synthesis tools

Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. In this paper we propose a fully automated design methodology for producing efficient FPGA implementations of PLC programs. The PLC programs can be prepared by automation experts using their familiar programming environments and the conversion to FPGA is done by automated high-level synthesis tools. The advantages of this approach are demonstrated on a number of standard industrial control applications.

Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis

This paper is a continuation of a previous work by the same authors concerning the use of automated high-level synthesis tools for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications requiring lots of numerical computations. High-level synthesis is based on powerful, commercial tools. Since most of these tools are not compatible with PLC development environments, custom translating software built by using standard compiler techniques, can be employed for converting PLC programs to a form that can be understood by the selected tools. Experimental results involving both fixed-point and floating point implementations of three well-known industrial control algorithms are presented.

A run-time reconfigurable fuzzy PID controller based on modern FPGA devices

Recent advances in device densities and the requirement for short time-to-market has made FPGA devices very popular for the implementation of general purpose electronic devices. Modern FPGA architectures offer the advantage of partial reconfiguration, which allows an algorithm to be partially mapped into a small and fixed FPGA device that can be reconfigured at run time, as the mapped application changes its requirements. Such a feature can be beneficial for modern control applications, that may require the change of coefficients, models and control laws with respect to external conditions. This paper presents an embedded run-time reconflgurable architecture for the design of a fuzzy logic PID controller. The proposed solution is both technically advanced and cost effective, offering flexibility, modularity and efficiency, without performance reduction.

An architectural exploration framework for efficient FPGA implementation of PLC programs

This paper presents an automated framework for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications, requiring lots of numerical computations. Based on previous experience, the proposed framework exploits Electronic System Level modeling methodologies and tools for high-level hardware synthesis. Since most of these tools are not compatible with PLC development environments, custom translating software built by using standard compiler techniques, can be employed for converting PLC programs to a form that can be understood by the selected tools. Furthermore, the translating software uses different coding templates to support microarchitectural level design trade-offs. Experimental results involving three well-known industrial control algorithms show that appropriate coding styles can offer 2x performance improvements, being simple and syntactically similar to Statement List code.

Recursive Synthesis of Robust Supervisory Controllers for Vector Discrete Event Systems

In this paper we present a generic recursive procedure for designing robust supervisory controllers for uncertain discrete event systems. This procedure is a direct extension of a corresponding methodology for continuous variable systems and its main advantage is that it allows us to replace a robust synthesis problem with a non robust synthesis problem and a number of analysis problems, which are usually easier to solve. The procedure is guaranteed to terminate in finite time although it does not always return a solution. The procedure can be used with different kinds of discrete event models. Here we investigate its application on vector discrete event systems. We focus on practical issues and propose systematic ways of dealing with the computational problems

Automated FPGA implementation methodology of PLC programs with floating point operations

Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. Also, FPGAs have been traditionally suited towards fast, fixed point calculations. This paper presents an automated methodology which addresses the first problem, by using language translators and hardware behavioral or high-level synthesis. For the second problem, different approaches to support floating point operations at the behavioral domain are thoroughly investigated. Overall, an efficient methodology for design space exploration of industrial control applications is proposed, using FPGA technology. The presented experiments show that design trade-offs can be easily explored and the desired solution for each application can be efficiently selected.

Program-based and model-based PLC design environment for multicore FPGA architectures

Digital design has been growing rapidly during the last years, offering advanced implementation solutions for a diversity of appliances and instruments, integrating different sensors and actuators. This has a great impact on embedded automation, where traditional Programmable Logic Controllers (PLCs) have been gradually replaced by high performance Embedded Controllers, Digital Signal Processor (DSP) chips and, more recently, power efficient Field Programmable Gate Arrays (FPGAs). Such new implementation platforms bring together efficient design methodologies, like model-based design and high-level or C level program-based design. In their turn, new design methodologies are accompanied by new design technologies like Intellectual Property (IP) based design and High-Level Synthesis (HLS). This paper presents a design environment that utilizes program-based and model-based design, for the development of PLC applications. Specifically, a tool flow is constructed that supports either the design of new control algorithms or the translation of existing algorithms into C. Then, HLS and FPGA implementation tools are adopted, to implement the selected algorithms as multicore, embedded designs, offering performance improvements and hardware utilization efficiency. Overall, the proposed methodology and underlying tool flow support a novel high productivity prototyping platform for digital control applications, with very promising future extension capabilities.

A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs?

Digital signal processing has emerged in every aspect of modern life, with different implementations found in appliances ranging from simple answering machines to high speed multimedia cloud routers. The design of such appliances requires a number of decision steps, based on diverse criteria like time-to-market, development cost, production cost, production volume, performance, power consumption and algorithm complexity, to name just a few. A crucial decision step is the use of a floating or fixed-point number representation. This paper presents a new paradigm for the design of floating point applications, based on modern hardware design techniques like electronic system level design and high-level synthesis, and the computing capabilities and power efficiency of modern FPGA devices. Specifically, it presents the design of a reusable, floating point, hardware operator library, starting from an open source software implementation. The advantages of this new paradigm is productivity improvement and ease of integration, through the use (or reuse) of C level input specifications, and performance improvements, by applying a set of specific C level hardware coding guidelines. As found through extensive experimentation, performance and area optimizations offered by these guidelines can be even more than 90%. Such results make the presented methodology an appealing and very promising design alternative.

Efficient C level hardware design for floating point biomedical DSP applications

Recent advances in embedded system design has increased their interference in different application domains, where software only solutions have prevailed. This new implementation platform require however quality of results in terms of speed, power and computational complexity, along with strict time-to-market schedules. Performance is sought by utilizing modern Field Programmable Gate Array (FPGA) devices, offering hundreds of GFLOPs with maximum power efficiency. Productivity is enforced with High-Level Synthesis (HLS) or Electronic System Level (ESL) or C-based hardware design methodologies, that offer an efficient abstraction level to boost-up early prototyping. However, just like the migration from schematics to Hardware Description Languages (HDLs) required specific coding styles for efficient hardware design, C-based hardware design also requires efficient coding guidelines to be followed. This paper presents a set of such coding guidelines, and evaluates their efficiency for FPGA based scientific, floating point arithmetic calculations. As found through extensive experimentation, the performance and area optimizations offered by efficient coding can improve the ones offered by HLS only, even more than 90%. So, while not every C program can be turned into hardware with the press of a button, efficient coded C programs can offer a profitable productivity boost.

A Safe Set Point Supervisor for MIMO Processes

In a previous paper we introduced a supervisory control framework for setting the operating point of an industrial process with unknown characteristics. Here we extend this methodology for the case of MIMO processes. The proposed supervisory control framework is agent-based and it involves modeling agents and intelligent agents. The modeling agents derive local steady-state models of the process during normal process operation by using various identification techniques, each of which corresponds to a different instantiation of our system. The intelligent agents are proposed to be implemented using finite automata units. The performance of the proposed scheme is illustrated through simulation results on well-known benchmark problems of chemical industry.