Ioannis Koutras

Construction of dual mode components for reconfiguration aware high-level synthesis

High-level synthesis has recently started to gain industrial acceptance, due to the improved quality of results and the multi-objective optimizations offered. One optimization area lately addressed is reconfigurable computing, where parts of a DFG are merged and mapped into coarse grained reconfigurable components. This paper presents an alternative approach, the construction of dual mode components which are exchanged with regular components in the resulting RTL architecture. The dual mode components are constructed by exhaustive search for dual mode functional primitives inside the datapath of complicated RTL components. Such components, like multipliers and dividers, that would remain idle in certain control steps, are able to work full-time in two different modes, without any reconfiguration overhead applied to the critical path of the application. The results obtained with different DSP benchmarks show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization.

Power-aware dynamic memory management on many-core platforms utilizing DVFS

Today multicore platforms are already prevalent solutions for modern embedded systems. In the future, embedded platforms will have an even more increased processor core count, composing many-core platforms. In addition, applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the embedded platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes the systems bottleneck. To cope with this dynamism and achieve better memory footprint utilization (low memory fragmentation) application developers resort to the usage of dynamic memory (heap) management techniques, by allocating and deallocating data at runtime. Moreover, overall power consumption is another key challenge that needs to be taken into consideration. Towards this, designers employ the usage of Dynamic Voltage and Frequency Scaling (DVFS) mechanisms, adapting to the applications computational demands at runtime. In this article, we propose the combination of dynamic memory management techniques with DVFS ones. This is performed by integrating, within the memory manager, runtime monitoring mechanisms that steer the DVFS mechanisms to adjust clock frequency and voltage supply based on heap performance. The proposed approach has been evaluated on a distributed shared-memory many-core platform composed of multiple LEON3 processors interconnected by a Network-on-Chip infrastructure, supporting DVFS. Experimental results show that by using the proposed method for monitoring and applying DVFS mechanisms the power consumption concerning dynamic memory management was reduced by approximately 37%. In addition we present the trade-offs the proposed approach. Last, by combining the developed method with heap fragmentation-aware dynamic memory managers, we achieve low heap fragmentation values combined with low power consumption.

Adaptive dynamic memory allocators by estimating application workloads

Modern applications are becoming more complex and dynamic and try to efficiently utilize the amount of available resources on the computing platforms. Efficient memory utilization is a key challenge for application developers, especially since memory is a scarce resource and often becomes systems bottleneck. Thus, the developers can resort to dynamic memory management, i.e., dynamic memory allocation and de-allocation, to efficiently utilize the memory resources. A high-performance adaptive memory allocator is presented in this paper. A memory allocator helps applications to manage more efficiently the memory space that operating systems bestow to them. In our approach, we tune the memory allocator at runtime by predicting the amount of memory to be requested. Experimental results obtained using applications from the PARSEC benchmark suite and dmmlib, a memory allocator framework written in C. Results show that adaptive memory allocators can improve the fragmentation problems leading to a more efficient memory usage.

Automated FPGA implementation methodology of PLC programs with floating point operations

Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. Also, FPGAs have been traditionally suited towards fast, fixed point calculations. This paper presents an automated methodology which addresses the first problem, by using language translators and hardware behavioral or high-level synthesis. For the second problem, different approaches to support floating point operations at the behavioral domain are thoroughly investigated. Overall, an efficient methodology for design space exploration of industrial control applications is proposed, using FPGA technology. The presented experiments show that design trade-offs can be easily explored and the desired solution for each application can be efficiently selected.

A reconfigurable IP characterization technique improving high-level synthesis results

Reconfigurable computing is a cost-effective alternative to technology shrinking in order to achieve higher performance in digital design, especially considering run time reconfiguration. Research in the field consists of new reconfig-urable architectures, either coarse-grain or fine-grain, and new methodologies to map applications onto them. Usually, top-down methodologies are proposed, that start from the applications dataflow graph and try to merge different parts into the same reconfigurable component. This paper presents a bottom-up approach, that searches available RTL component libraries for primitives that can be connected in alternative ways and generate new components, with different modes of functionality. Such components, called morphable components, are designed to impose the minimum accepted area and timing overhead, without any reconfiguration overhead. The great advantage of the bottom-up approach is that it can be integrated easily with existing design methodologies and tools, offering great overall performance improvements. The results obtained with different DSP benchmarks in a high-level synthesis environment show an average performance gain of 15%, without any practical datapath area increase, offering uniform and balanced resource utilization.

On supporting rapid prototyping of embedded systems with reconfigurable architectures

Abstract Reducing time-to-market while improving product quality is a big challenge. This paper proposes a software-supported framework for rapid prototyping that offers a concurrent fast hardware/software system-level design. The introduced framework enables the constant evaluation and verification of the prototype under development, while it provides automatic functionality mapping to hardware via High-Level Synthesis techniques. We evaluate our framework and its software instantiation with a computer vision algorithm. Based on our experimentation, we show that our approach reduces the development time by almost 64×, it prunes the hardware design space by 34×, while maintaining designs that trade-off high Quality-of-Report on the Pareto frontier.

Improving Dynamic Memory Allocation on Many-Core Embedded Systems With Distributed Shared Memory

Memory management on many-core architectures is a major challenge for improving the overall system performance. Memory resources are distributed over nodes for faster local accesses. Dynamic workloads heavily depend on memory requests and inefficient memory management leads to severe bottlenecks and performance degradation. In this paper, we focus on optimizing dynamic memory allocation on such platforms and present a scalable, microcode-accelerated distributed dynamic memory manager. The proposed manager exploits the presence of a hardware accelerator while offering a C application programming interface to application developers. Experimental results show performance gains on average 10% compared to allocators written purely in C and sufficient scalability as platform size increases.

Heap Management for Trusted Operating Environments

Dynamic memory managers are responsible for organizing the dynamically allocated data in memory and also servicing the application’s memory requests (allocation/deallocation) at run-time. In today’s trusted embedded systems, dynamic memory management is a mechanism implemented in order to interact with modern applications. However, the majority of these applications are not self secured. The combination of scripting languages, fast development and user centralized environments ends up with applications full of security flaws. In this chapter, we will present the Dynamic Memory Management (DMM) design space and all the orthogonal decision trees including heap protection actions. Also, we will present methods for securing memory allocators for modern embedded systems.

BIT-width exploration over 3D architectures using high-level synthesis

The interface between storage and processing has always been one of the main bottlenecks to the performance and energy efficiency in embedded system design. In this paper we are exploring the potential to increase the bandwidth through this interface by increasing the number of physical connections. This option becomes available using 3D stacking technologies. Our aim is to evaluate the power efficiency of a wider memory interface at the level of the complete system, including the memory, the interface circuitry itself and the processing elements. We want to understand whether this additional bandwidth can be efficiently utilized by the processing elements and enable an overall lower power and higher throughput solution compared to state-of-the-art system implementations.