George Economakos

FPGA implementation of PLC programs using automated high-level synthesis tools

Although the performance of traditional PLC technology is adequate for the majority of industrial automation and control tasks, there exist a number of demanding applications, which need more powerful alternatives. One such alternative, which has received considerable research interest in recent years, is the implementation of control algorithms on FPGAs. An inherent difficulty of this approach is that it requires expertise in both industrial automation and FPGAs. In this paper we propose a fully automated design methodology for producing efficient FPGA implementations of PLC programs. The PLC programs can be prepared by automation experts using their familiar programming environments and the conversion to FPGA is done by automated high-level synthesis tools. The advantages of this approach are demonstrated on a number of standard industrial control applications.

Behavioral synthesis with systemC

Having to cope with the continuously increasing complexity of modern digital systems, hardware designers are considering more and more seriously language based methodologies for parts of their designs. Last year the introduction of a new language for hardware descriptions, the SystemC C++ class library, initiated a closer relationship between software and hardware descriptions and development tools. This paper presents a synthesis environment and the corresponding synthesis methodology, based on traditional compiler generation techniques, which incorporate SystemC, VHDL and Verilog to transform existing algorithmic software models into hardware system implementations. Following this approach, reusability of software components is introduced in the hardware world and time-to-market is decreased, as shown by experimental results.

Bit level architectural exploration technique for the design of low power multipliers

In this paper a new technique for the design of combinational circuits for low power is introduced. The basic idea is to bypass blocks of logic when their function is not required, using low delay and area overhead components (transmission gates). The internal state of these blocks is kept unchanged, so the switching activity of the circuit is minimized, resulting to low power consumption. While this ideas is applicable to array multipliers, the reduced area of the Wallace tree multiplier is a temptation for the designer. Therefore, a mixed architecture, using both traditional and bypass techniques is proposed, which outperforms the Wallace tree in both power consumption and timing, with a 15%-20% extra area penalty

Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths

This paper introduces a design technique for coarse-grained reconfigurable architectures targeting digital signal processing (DSP) applications. The design procedure is analyzed in detail and an area-time-power efficient reconfigurable kernel architecture is presented. The proposed technique inlines flexibility into custom carry-save (CS) arithmetic datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a transformation, called uniformity transformation, imposed on the basic architectures of CS-multipliers and CS-chain-adders/subtractors. Experimental results including quantitative and qualitative comparisons with existing reconfigurable arithmetic cores and exploration results of the proposed reconfigurable architecture are provided.

An attribute grammar approach to high-level automated hardware synthesis

Abstract Attribute grammars have been used extensively in every phase of traditional compiler construction. Since some of these phases have also been used in automated hardware synthesis (hardware compilation), attribute grammars can be effectively adopted to handle the two major tasks of high-level hardware synthesis, operation scheduling and hardware allocation, implementing various algorithms. This paper presents an attribute grammar driven scheduling system, as a more abstract way of handling the whole high-level hardware synthesis task, while maintaining the desired functionality by the utilization of existing and well-tested tools and techniques transferred from traditional compiler construction.

High Performance and Area Efficient Flexible DSP Datapath Synthesis

This paper presents a new methodology for the synthesis of high performance flexible datapaths, targeting computationally intensive digital signal processing kernels of embedded applications. The proposed methodology is based on a novel coarse-grained reconfigurable/flexible architectural template, which enables the combined exploitation of the horizontal and vertical parallelism along with the operation chaining opportunities found in the applications behavioral description. Efficient synthesis techniques exploiting these architectural optimization concepts from a higher level of abstraction are presented and analyzed. Extensive experimentation showed average latency and area reductions up to 33.9% and 53.9%, respectively, and higher hardware area utilization, compared to previously published high performance coarse-grained reconfigurable datapaths.

Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis

This paper is a continuation of a previous work by the same authors concerning the use of automated high-level synthesis tools for obtaining high-performance FPGA implementations of industrial automation and control algorithms coded as PLC programs. The proposed method is mainly targeting demanding applications requiring lots of numerical computations. High-level synthesis is based on powerful, commercial tools. Since most of these tools are not compatible with PLC development environments, custom translating software built by using standard compiler techniques, can be employed for converting PLC programs to a form that can be understood by the selected tools. Experimental results involving both fixed-point and floating point implementations of three well-known industrial control algorithms are presented.

Flexible Datapath Synthesis through Arithmetically Optimized Operation Chaining

Datapath synthesis incorporating complex operation templates has been proven extremely efficient especially for the Digital Signal Processing (DSP) application domain.However, only architectural level optimizations have been reported for the specification and implementation of the operation templates. This paper introduces the consideration of arithmetic level optimizations for template based datapath synthesis. A high performance architecture for the implementation of DSP kernels is presented. It is based on flexible and arithmetically optimized components able to perform a large set of operation templates. A synthesis methodology for optimized mapping of DSP kernels onto the proposed architecture is also presented. Experimental results are reported showing significant gains in execution time, active chip area and power dissipation in comparison to previously published flexible template-based data paths.

AGENDA: an attribute grammar driven enviornment for the design automation of digital systems

Attribute grammars have been used extensively in every phase of traditional compiler construction. Recently, it has been shown that they can also be effectively adopted to handle scheduling algorithms in high-level synthesis. Their main advantages are modularity and declarative notation in the development of design automation environments. In this paper, past results are further elaborated and more scheduling techniques are presented and implemented in a flexible environment for the design automation of digital systems. This novel approach can be proven valuable for fast evaluation of new algorithms and techniques in the field.

ECG handling on a telemedicine platform

In this paper we present the principles of a new platform developed for handling ECG signals in a telemedicine setting. We focus on three basic services: an ECG file management system (acquisition, storage, transmission); ECG-oriented teleconferencing; and realtime transmission of ECGs over the telephone network. This work has been carried out in the context of national and EU-sponsored projects. Its main purpose was to help patients from remote or isolated areas, like small islands, with insufficient health-care services, to get appropriate and experienced medical care directly from large central hospitals. We present the design and the basic operations of the ECG handling system.