Christoph Adelmann

Flexible and robust capping-metal gate integration technology enabling multiple-VT CMOS in MuGFETs

We report, for the first time, a comprehensive study on various capping integration options for WF engineering in MuGFET devices with TiN gate electrode: HfSiO/cap/TiN, cap/HfSiO/TiN and HfSiO/TiN/cap/TiN vs. reference deposition sequence HfSiO/TiN (cap = Al2O3 for pmos, and Dy2O3 or La2O3 for nmos). We show that: 1) low-VT values (Lt 0.3 V) are achieved for both nmos and pmos, with excellent process control and device behavior down to Lg ap 50 nm and WFIN ap 20 nm, for optimized gate stack configurations; 2) inserting a cap layer in-between TiN layers instead of HfSiO/cap/TiN leads to improved mobility, reduced CET without impacting JG, similar noise response and improved BTI behavior, with correction of the abnormal PBTI degradation seen for HfSiO/DyO/TiN. Is also enables simplified and more robust CMOS co-integration of low- and med-VT devices in the same wafer, avoiding loss in CET and damage of the host dielectric with the cap removal process.

Aqueous chemical solution deposition of ultrathin lanthanide oxide dielectric films

Hasselt Univ, Mat Res Inst, Lab Inorgan & Phys Chem, B-3590 Diepenbeek, Belgium. IMEC vzw, Div IMOMEC, B-3590 Diepenbeek, Belgium. IMEC vzw, B-3001 Heverlee, Belgium. Katholieke Univ Leuven, Dept Chem, B-3001 Heverlee, Belgium. XIOS Hogesch Limburg, Dept Ind Sci & Technol IWT, B-3590 Diepenbeek, Belgium.Van Bael, MK, Hasselt Univ, Mat Res Inst, Lab Inorgan & Phys Chem, B-3590 Diepenbeek, Belgium.marlies.vanbael@uhasselt.be jules.mullens@uhasselt.be

Aqueous chemical solution deposition : Fast screening method for alternative high-k materials applied to Nd2O3

Material screening of gate dielectrics for complementary metal oxide semiconductor applications is often complicated by the inability to deposit test samples. We examine the aqueous chemical solution deposition (CSD) technique as a simple, inexpensive, and fast technique to deposit thin metal-oxide layers. We deposited Nd 2 O 3 layers on 1.2 nm SiO 2 . The thinnest stack (7.2 nm) yielded an equivalent oxide thickness (EOT) of 3.1 nm with a gate-leakage current of 1.4 X 10 -6 A/cm 2 at V FB - 3 V. EOT scales linearly with physical thickness, allowing a k-value extraction, approximately 14. Our results suggest that aqueous CSD is a viable method for fast gate-dielectrics screening.

Equivalent Oxide Thickness Reduction for High-k Gate Stacks by Optimized Rare-Earth Silicate Reactions

Equivalent oxide thickness (EOT) scaling still remains one of the main facilitators to increase transistor performance. The use of rare-earth (RE) elements has been shown to effectively increase permittivity of the gate-stack interfacial layer between substrate and high-k dielectric, reducing its EOT contribution. In this paper, we have studied the optimal RE-to-SiO 2 ratio using Dy 2 O 3 as a test case. Capacitance-voltage and leakage current-voltage measurements were performed on Pt-gated capacitors with a SiO 2 /Dy 2 O 3 /Sc-doped HfO 2 gate stack and varying ratios of Dy 2 O 3 to SiO 2 after a 1000°C anneal. Optimal EOT-leakage performance was found for a Dy 2 O 3 -to-SiO 2 ratio of ∼0.5 to 0.6.

Low VT metal-gate/high-k nMOSFETs — PBTI dependence and V T Tune-ability on La/Dy-capping layer locations and Laser annealing conditions

This paper provides a comprehensive study of the abnormal PBTI behaviors recently observed in La/Dy-capped high-k films in low-VT nMOSFETs. We found that process details in thermal budget (or dielectric intermixing) and oxygen content of the metal trigger the onset of these abnormalities. The DeltaVT relaxation during the PBTI recovery period induced by bulk trapping/de-trapping is believed to be oxygen vacancies related, and can be suppressed either by reducing dielectric intermixing with lower laser anneal powers (La above or below HK), or by increasing the oxygen concentration, i.e., TaCNO metal electrode instead of TaCN (La above HK). Putting La below HK can result in a similar VT tune-ability with less thermal budget for intermixing with the IL (with superior PBTI), without loss of current drive-ability. We propose Ta2C/HK/LaO/IL + LLP anneals as an optimum nFETs stack configuration for practical CMOS integration.

AVD and MOCVD TaCN-based Films for Gate Metal Applications on High k Gate Dielectrics

After overcoming the integration issues for the last few years, the insertion of high k dielectrics and metal gate stacks are now becoming obvious into probably 45nm and surely 32nm technology node. As the devices are scaled down, metal gate technology in conjunction with high-k gate dielectric are critical to replace conventional nitrided-oxide/poly-Si gate stacks. Advanced CMOS requires compatibility for a single or dual metal gate process with suitable work-functions to have the right Vt for nMOS and pMOS respectively. Obtaining pMOS solutions has been a challenge to meet band-edge work-function of >5.2eV.

EUV lithography imaging using novel pellicle membranes

EUV mask protection against defects during use remains a challenge for EUV lithography. A stand-off protective membrane – a pellicle – is targeted to prevent yield losses in high volume manufacturing during handling and exposure, just as it is for 193nm lithography. The pellicle is thin enough to transmit EUV exposure light, yet strong enough to remain intact and hold any particles out of focus during exposure. The development of pellicles for EUV is much more challenging than for 193nm lithography for multiple reasons including: high absorption of most materials at EUV wavelength, pump-down sequences in the EUV vacuum system, and exposure to high intensity EUV light. To solve the problems of transmission and film durability, various options have been explored. In most cases a thin core film is considered, since the deposition process for this is well established and because it is the simplest option. The transmission specification typically dictates that membranes are very thin (~50nm or less), which makes both fabrication and film mechanical integrity difficult. As an alternative, low density films (e.g. including porosity) will allow thicker membranes for a given transmission specification, which is likely to improve film durability. The risk is that the porosity could influence the imaging. At imec, two cases of pellicle concepts based on reducing density have been assessed : (1) 3D-patterned SiN by directed self-assembly (DSA), and (2) carbon nanomaterials such as carbon nanotubes (CNT) and carbon nanosheets (CNS). The first case is based on SiN membranes that are 3D-patterned by Directed Self Assembly (DSA). The materials are tested relative to the primary specifications: EUV transmission and film durability. A risk assessment of printing performance is provided based on simulations of scattered energy. General conclusions on the efficacy of various approaches will provided.

Multiple-Vt FinFET devices through La 2 O 3 dielectric capping

In this work, the possibility of achieving low Vt nMOS FinFET transistors through the use of a La₂O₃ dielectric cap, and the ability of co-integrating La₂O₃ capping with medium and low Vt pFinFET devices are investigated. A significant improvement in device performance was shown for thin La₂O₃ capping with CVD TaN electrode.

Properties and performance of EUVL pellicle membranes

EUV mask protection during handling and exposure remains a challenge for high volume manufacturing using EUV scanners. A thin, transparent membrane can be mounted above the mask pattern so that any particle that falls onto the front of the mask is held out of focus and does not image. The fluoropolymer membranes that are compatible with 193nm lithography absorb too strongly at the 13.5nm EUV exposure wavelength to be considered. Initially, the industry planned to expose EUV masks without any pellicle; however, the time and cost of fabricating and qualifying an EUV mask is simply too high to risk decimating wafer yield each time a particle falls onto the mask pattern. Despite the challenges of identifying a membrane for EUV, the industry has returned to the pellicle concept for protection. EUVL pellicles have been in development for more than a decade and reasonable options exist. Meeting all pellicle requirements is difficult, so this type of risk-mitigation effort is needed to ensure that there is a viable high-volume manufacturing option. This paper first reviews the desired membrane properties for EUVL pellicles. Next, candidate materials are introduced based on reported properties and compatibility with fabrication. Finally a set of candidate membranes are fabricated. These membranes are screened using a simplified set of tests to assess their suitability as an EUV pellicle. EUV transmission, film stress, and film durability data are included. The results are presented along with general guidelines for pellicle membrane properties for EUV manufacturing.

Second-harmonic generation as characterization tool for Ge/high-k dielectric interfaces

Because the germanium native oxide constitutes a poor dielectric, building metal oxide semiconductors (MOS) gate stacks on Ge requires passivation of the interface between the dielectric and the Ge channel. Different approaches to perform this passivation are available: GeO2 growth prior to high-k depositing, sulphur passivation, etc. The interface properties of these MOS stacks are important, because they determine the electrical properties of the whole structure. Dangling bonds introduce extra energy levels within the band gap, which results in a loss of efficiency in switching a MOS - field effect transistor on and off. Fixed charges near the interface enlarge the voltage needed for switching between on and off state as well. Hence, characterizing these interfaces is a key challenge in semiconductor fabrication. This can for example be achieved using Second Harmonic Generation (SHG) to probe the interface, because SHG is an inherent surface and interface sensitive technique. In this work, we present SHG as an promising surface and interface characterization tool for semiconductors for passivated germanium samples. Different SHG responses are shown for germanium samples with a sulphur passivated Ge or high-k dielectric on top of Si. We show that the oxide layer as such is not probed by SHG and that different bonds over the Ge/oxide interface result in a difference SHG response.