Christoph Pichler

A new wideband compact model for spiral inductors in RFICs

A new wide-band compact model for planar spiral inductors on lossy silicon substrate is presented. Transformer loops are used in the series branch of the equivalent circuit model to include the effects of the frequency-dependent losses, in particular eddy-current loss in the silicon substrate. The new compact model and the standard 9-element model are extracted from measurement data of a typical 1.5-nH spiral fabricated on a low-resistivity CMOS substrate over a frequency range of 0.1 to 10 GHz. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new model are in excellent agreement with the measured results.

Wide-band compact modeling of spiral inductors in RFICs

A new wide-band compact modeling methodology for planar spiral inductors on lossy silicon substrate is presented. The new ideal lumped-element equivalent circuit model employs transformer loops in the series branch to include the effects of the frequency-dependent losses, in particular eddy-current loss in the bulk silicon substrate. A robust automated extraction procedure is employed to extract the element values of the new compact model. The new automated modeling methodology has been applied to a typical 1.5 nH spiral fabricated on a low-resistivity CMOS substrate. The frequency-dependent series resistance and inductance as well as the quality factor obtained with the new wideband model are in excellent agreement with the measured results over a 10 GHz bandwidth.

On the lower bounds of CMOS supply voltage

Abstract The lower bounds of the supply voltage V DD of ultra-low-power CMOS technologies are investigated under the constraints of standard digital circuit design. After discussing the peculiarities of ultra-low-power CMOS processes, low-voltage device operation, and scaling benefits, the lower limits for V DD are narrowed down from two sides. First, a simple inverter based on idealised transistors is investigated analytically to determine a set of absolute lower bounds of V DD for a set of given design constraints, i.e. minimum gain and noise margins. Next, the feasibility and performance of ultra-low-power CMOS technologies are investigated using process and device simulation, followed by post-processing of the simulated I - V and capacitance data, to determine a set of achievable lower bounds of V DD . On the basis of state-of-the-art processes and special scaling, a set of possible ultra-low-power CMOS processes was developed and numerically analysed on the gate level. These numerical data are then related to the analytical results.

VISTA-user interface, task level, and tool integration

Succeeding an earlier paper on the data level, the Viennese Integrated System for Technology CAD Applications (VISTA), an integration and development system for Technology CAD, is presented. Starting with a short overview of TCAD methodology and existing integrated systems, portability and comprehensibility are postulated as key considerations and an application-framework architecture is proposed. The design of VISTAs user interface and task level, presented next, adheres strictly to these guidelines. To enable the cooperation of independent simulation tools, an automatic triangulation-based service is provided by VISTA to resolve inconsistencies in wafer representations. A final example shows how three different simulators, integrated by the framework are used to simulate a planarized, trench-isolated 0.25 /spl mu/m CMOS process. >

High-level TCAD task representation and automation

With shrinking device dimensions and decreasing product-development cycles, fully-automated TCAD analysis of complete semiconductor processes and devices is becoming increasingly important. We present a programmable simulation environment for VLSI technology analysis, focusing on high-level tasks including response surface modeling (RSM) and optimization. Based on process and device simulation capabilities with heterogeneous simulation tools, split-lot experiments can be defined for fabrication process flows and simulation sequences. The parallel and distributed execution of independent split tree branches allow a fast computation of large-scale experiments. A persistent run data base keeps all simulation results and prevents unnecessary re-computations. Special emphasis has been put on establishing in an object-oriented fashion a uniform and easy-to-use interface for applications and extensions supplied by the user. the combination of a comfortable, intuitive visual user interface with the flexibility and versatility of a high-level programming language for TCAD applications results in a powerful tool for tcad integration, development, and production use.

Simulation of complete VLSI fabrication processes with heterogeneous simulation tools

An integrated environment for the simulation of VLSI fabrication processes is presented. Emphasis is put on automated operation to achieve maximum efficiency in TCAD deployment. Addressing the increasing number and diversity of process steps in state-of-the-art semiconductor fabrication processes, mechanisms have been devised to support the smooth, automatic interaction of heterogeneous simulation tools with multiple data formats in the context of large-scale experiments for global calibration, device optimization, and yield improvement tasks. For maximum versatility, the operation of the environment is either controlled via a graphical user interface, a batch file, or a combination of the two. It is possible to submit predefined analysis tasks for background execution, while still being able to monitor and control operation and to access and view simulation data interactively. Split-lot experiments are performed on workstation clusters in parallel operation, delivering the desired results in the shortest possible time. The TCAD environment presented offers server functionality for running large number of complex simulations. At the same time, it supports the design and seamless integration into the environment of client task applications.

VLSI performance analysis method for low-voltage circuit operation

An efficient and accurate method for VLSI performance analysis is presented. It takes measured or simulated IV and capacitance data as input and yields the noise margins and delay parameters directly without any intermediate parameter extraction, avoiding the common errors of compact modeling. The method is applied to the IV/C data of an ultra-low-power CMOS process and the results are then verified by a rigorous device-level simulation of ring oscillators.