Christoph Trummer

Simulation based verification of energy storage architectures for higher class tags supported by energy harvesting devices

Abstract Enhanced RFID tag technology especially in the UHF frequency range provides an extended functionality like high operating range and sensing and monitoring capabilities. Such complex functionality requires extended system structures including data acquisition units, real time clocks and active transmitters that cause a high energy consumption of the tag and require an on-board energy store (battery). Since the lifetime is a key parameter for the reliability of an RFID system, the energy budget of the higher class tag has to be as balanced as possible. This can be achieved by using energy harvesting devices as additional power supplies. The PowerTag 1 project and thus this paper propose special energy storage structures, which interface energy harvesting devices and deal with their special requirements to be used with battery-driven higher class UHF RFID tags. Different implementation variants of such structures are compared by using accurate simulation models of various parts of the system. The results of the simulation are compared to provided manufacturer performance parameters of a state-of-the-art higher class UHF RFID system.

Automatic Test Generation From Semi-formal Specifications for Functional Verification of System-on-Chip Designs

In common design flows of system-on-chip (SoC) designs functional verification requires 70% of the entire design effort. Most of the effort for functional verification is spent on finding and creating adequate testcases to verify that the modeled design corresponds to its specification. This is done manually, since automatic test case generation from the specification is often not possible due to the informal, non-machine readable structure of the specification document. Formal specification languages would ease the parsing process, however, these formats are difficult to use by system engineers from different domains. A promising trade-off are semi-formal specification formats, which are both easy-to-parse and easy-to-use. The SIMBA project focuses on semi-formal use case-based specification formats, which are used to automatically generate a transaction-based SystemC verification platform. Finally, these SystemC testcases are simulated together with the System-under- Verification (SuV) to verify that it fulfills the given specification. This results in a novel design methodology regarding requirements elicitation and automatic test case generation. A demonstration is given by applying this methodology to a SystemC RFID controller model. It is shown that the demonstrated approach automates and improves the functional verification of SoCs.

Simulation Based Verification of Energy Storage Architectures for Higher Class Tags supported by Energy Harvesting Devices

Enhanced RFID tag technology especially in the UHF frequency range provides extended functionality like high operating range and sensing and monitoring capabilities. Such functionality requiring extended system structures including data acquisition units, real time clocks and active transmitters causes a high energy consumption of the tag and requires an on board energy store (battery). As a key parameter of the reliability of an RFID system is the lifetime, the energy budget of the higher class tag has to be as balanced as possible. This can be achieved by using energy harvesting devices as additional power supply. The PowerTag1 project and thus this paper proposes special energy storage structures interfacing energy harvesting devices and dealing with their special requirements for the use with battery-driven higher class UHF RFID tags. Different implementation variants of such structures are compared by using accurate simulation models of the various parts of the system. The results of the simulations are compared to manufacturer given and guaranteed system performance parameters of a state-of-the-art higher class UHF RFID system.

A software performance simulation methodology for rapid system architecture exploration

The performance simulation of embedded system designs is often a time consuming process. Whereas the simulation performance of hardware models depends on the chosen abstraction level, the software part is usually simulated with a slow instruction-set-simulator (ISS), which greatly limits the entire simulation speed. In this paper we solve this problem by presenting a highly automated methodology developed in the SIMBA project, which replaces the ISS simulation with a faster performance simulation of a delay-annotated software model suitable for architecture exploration of embedded systems. We use the assembler code from the target cross-compiler and the processor datasheet to automatically generate a SystemC model, which consists of the original software code annotated with additional delay information for each C-code statement to consider the timing behavior of the software. This also encompasses micro-architectural effects like different cache/memory access times and pipeline effects. The SystemC simulation of the model provides accurate information on the timing behavior of the software close to the software execution time on the target processor. We use a sample software C-code to prove our methodology and compare it with an ISS simulation. It shows that our methodology provides a several times faster performance simulation of the software with sufficient accuracy regarding timing, cache, pipeline and memory accesses as it is required for the architecture exploration of embedded systems.

Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801

For System-on-Chips (SoCs) the most critical design constraint is power dissipation. Therefore, power aware design should be introduced at early stages of SoC design where it has the highest benefits for power reduction. This also lowers the design complexity and verification effort. Until recently, capabilities to describe and verify the power design early were inadequate which often led to late re-design. Lately, the IEEE 1801 Standard for Design and Verification of Low Power Integrated Circuits, an extension of the Unified Power Format (UPF) was approved. This work uses the new IEEE 1801 standard to describe power aware design. The power design is automatically translated into an executable hierarchy parallel to the system design. Simulation results from system and power design are used to automatically verify the SoCs power aware design against its specifications.

Searching Extended IP-XACT Components for SoC Design Based on Requirements Similarity

To counter todays rising complexity in system-on-chip (SoC) design intellectual property (IP) components are reused. These IP components are models of system parts (e.g., CPU, memory, bus) used in SoC design. In IP libraries many different of such predesigned components are available. However, finding and selecting functionally suitable ones is difficult and laborious. Additionally, certain nonfunctional constraints need to be considered when searching for IP. However, these additional constraints such as power dissipation, performance and verification status are rarely considered in currently available IP representation formats. This paper introduces our innovative approach for searching suitable components in the IP library. Therefore, IP-XACT, a common IP representation format, is extended with relevant information. The IP represented in this way is managed in a library which utilizes our novel selection process taking similarities between system and component requirements into account. The result is a ranking of the best-suited components for reuse in the current system-under-design. To demonstrate our approach a case study is performed on a SoC. With our methodology a ranking of components matching the systems requirements and constraints is generated.

Automated simulation-based verification of power requirements for Systems-on-Chips

Today power dissipation is the most important constraint for Systems-on-Chips (SoCs). Consequently, it is necessary to consider power in the requirements of mobile, battery-powered devices in which SoCs are often used. These power requirements describe battery lifetime, power constraints and low-power states. Verification ensures that the system fulfills the power requirements. However, verifying all requirements of the complex SoC design needs considerable effort. We introduce a methodology to reduce the verification effort through a high degree of automation. Our novel approach to verify battery lifetime, power constraints and the power aware design comprises three parts. First, a semi-formal use case format unifies specification of power and system requirements. Second, these specifications are used to automatically derive test cases and to generate a verification environment. Third, fast simulation and power estimation are employed to verify battery lifetime, power constraints and the power aware design against the requirements.

Verification methodology for battery lifetime requirements of higher class UHF RFID tags

Todays higher class tags usually are powered by batteries. The batterys capacity and the applications power demand influence the operational lifetime of the tag. Therefore, the designated application and lifetime requirement have to be kept in mind when designing a higher class tag. Moreover, the lifetime requirement needs to be verified in order to ensure the application will be successful. However, verification of the lifetime requirement is usually a very complex task. A verification environment for the application and its lifetime requirement needs to be created manually. After simulation with a battery model the results can be compared to the requirements document. Due to the complex and time-consuming nature of verification this often results in later time-to-market and increasing costs. In this work we present a novel, highly automated methodology to verify battery lifetime requirements. From the requirements document of the higher class UHF RFID tag a verification environment is created automatically. After power estimation is performed a battery model can be connected to the automatically generated lifetime verification environment. Finally, simulation is performed to verify whether the higher class UHF RFID tag fulfills the lifetime requirement of the application. The main benefit of our methodology is a decrease in the verification effort due to the high degree of automation in the creation of the verification environment. Moreover, simulation time is decreased which enables faster exploration of various batteries. This results in faster time-to-market and a reduction of costs.

Specification-based Verification of Embedded Systems by Automated Test Case Generation

It is time and resource intensive to derive test cases manually from the requirements specification to fully verify that the embedded system design fulfills its specification. However, automatic parsing to generate test cases is often not possible due to the informal, non-machine readable structure of the specification document. Formal specification languages would ease the parsing process, however they are difficult to use and rarely accepted. A promising trade-off are semi-formal specification languages, which are both easy-to-parse and easy-to-use.

A component selection methodology for IP reuse in the design of power-aware SoCs based on requirements similarity

To counter todays rising complexity in System-on-Chip (SoC) design intellectual property (IP) cores are reused. In libraries often many different pre-designed components are available and selecting suitable IP is difficult and laborious. Power consumption is a key constraint in mobile devices, where SoCs are often used. Therefore, it is important to consider power when selecting components for reuse in the current SoC design. This paper introduces our approach to support component search and selection. Initially, a repository and container for IP is presented. Onto our repository the novel component selection methodology is applied. It considers constraints and properties of IP. Then it performs a similarity analysis between system and component requirements. The result is a ranking of the best-suited components for reuse in the current system under design. To demonstrate our approach a case study is performed on a SoC. With our methodology ranking of components matching the system requirements and constraints is generated. Our work is part of the SIMBA1 project which focuses on simulation-based requirements testing of power-aware SoCs.