Damian Dalton

Simulation-based verification of power aware System-on-Chip designs using UPF IEEE 1801

For System-on-Chips (SoCs) the most critical design constraint is power dissipation. Therefore, power aware design should be introduced at early stages of SoC design where it has the highest benefits for power reduction. This also lowers the design complexity and verification effort. Until recently, capabilities to describe and verify the power design early were inadequate which often led to late re-design. Lately, the IEEE 1801 Standard for Design and Verification of Low Power Integrated Circuits, an extension of the Unified Power Format (UPF) was approved. This work uses the new IEEE 1801 standard to describe power aware design. The power design is automatically translated into an executable hierarchy parallel to the system design. Simulation results from system and power design are used to automatically verify the SoCs power aware design against its specifications.

Searching Extended IP-XACT Components for SoC Design Based on Requirements Similarity

To counter todays rising complexity in system-on-chip (SoC) design intellectual property (IP) components are reused. These IP components are models of system parts (e.g., CPU, memory, bus) used in SoC design. In IP libraries many different of such predesigned components are available. However, finding and selecting functionally suitable ones is difficult and laborious. Additionally, certain nonfunctional constraints need to be considered when searching for IP. However, these additional constraints such as power dissipation, performance and verification status are rarely considered in currently available IP representation formats. This paper introduces our innovative approach for searching suitable components in the IP library. Therefore, IP-XACT, a common IP representation format, is extended with relevant information. The IP represented in this way is managed in a library which utilizes our novel selection process taking similarities between system and component requirements into account. The result is a ranking of the best-suited components for reuse in the current system-under-design. To demonstrate our approach a case study is performed on a SoC. With our methodology a ranking of components matching the systems requirements and constraints is generated.

Automated simulation-based verification of power requirements for Systems-on-Chips

Today power dissipation is the most important constraint for Systems-on-Chips (SoCs). Consequently, it is necessary to consider power in the requirements of mobile, battery-powered devices in which SoCs are often used. These power requirements describe battery lifetime, power constraints and low-power states. Verification ensures that the system fulfills the power requirements. However, verifying all requirements of the complex SoC design needs considerable effort. We introduce a methodology to reduce the verification effort through a high degree of automation. Our novel approach to verify battery lifetime, power constraints and the power aware design comprises three parts. First, a semi-formal use case format unifies specification of power and system requirements. Second, these specifications are used to automatically derive test cases and to generate a verification environment. Third, fast simulation and power estimation are employed to verify battery lifetime, power constraints and the power aware design against the requirements.

Reducing the communication bottleneck via on-chip cosimulation of gate-level HDL and C-models on a hardware accelerator

This paper presents a hardware acceleration system based on a gate-level accelerator and an on-chip microprocessor enabling co-simulation of C-models with gate-level modules on the accelerator. This solution tackles the communication bottleneck that occurs when using hardware accelerators or emulators to speed up simulation. We analyze this bottleneck for the APPLES gate-level hardware accelerator and present the speedup that can be achieved by a prototype of the PowerPC-APPLES accelerator implemented on a Virtex2Pro FPGA on a PCI card.

A special purpose hybrid SIMD processor for logic event simulation

This paper introduces a hybrid associative memory/SIMD parallel processor, APPLES, which has been specifically designed for logic simulation. It reviews the computational structure which permits parallel execution of logic gate evaluations in memory. This facilitates fine grain execution on a massive scale of the basic tasks inherent in VLSI logic simulation. Furthermore, unlike other SIMD approaches the simulation is not limited to a unit delay model, complex delays such as inertial delays are permissible. The processor has been implemented in Verilog and assessed using ISCAS-85 benchmark. Gate evaluation is executed in constant time, whereas updating fan-out lists expands with circuit size. However, the APPLES architecture enables this latter task to be parallelised subject to various system parameters. The most important constraint is identified as the fan-out memory access time relative to the scan rate of the associative memory.

Verification methodology for battery lifetime requirements of higher class UHF RFID tags

Todays higher class tags usually are powered by batteries. The batterys capacity and the applications power demand influence the operational lifetime of the tag. Therefore, the designated application and lifetime requirement have to be kept in mind when designing a higher class tag. Moreover, the lifetime requirement needs to be verified in order to ensure the application will be successful. However, verification of the lifetime requirement is usually a very complex task. A verification environment for the application and its lifetime requirement needs to be created manually. After simulation with a battery model the results can be compared to the requirements document. Due to the complex and time-consuming nature of verification this often results in later time-to-market and increasing costs. In this work we present a novel, highly automated methodology to verify battery lifetime requirements. From the requirements document of the higher class UHF RFID tag a verification environment is created automatically. After power estimation is performed a battery model can be connected to the automatically generated lifetime verification environment. Finally, simulation is performed to verify whether the higher class UHF RFID tag fulfills the lifetime requirement of the application. The main benefit of our methodology is a decrease in the verification effort due to the high degree of automation in the creation of the verification environment. Moreover, simulation time is decreased which enables faster exploration of various batteries. This results in faster time-to-market and a reduction of costs.

The Speedup Performance of an Associative Memory Based Logic Simulator

As circuits increase in size and complexity, there is an ever demanding requirement to accelerate the processing speed of logic simulation. Parallel processing has been perceived as an obvious candidate to assist in this goal and numerous parallel processing systems have been investigated. Unfortunately, large speedup figures have eluded these approaches. A large communication overhead due to basic passing of values between processors, elaborate measures to avoid or recover from deadlock and load balancing techniques, is the principal barrier to achieving high speedup. This paper presents an Associative memory architecture which is the basis of a machine APPLES(Associative Parallel Processor for Logic Event Simulation), specifically designed for parallel discrete event logic simulation. A scan mechanism replaces inter-process communication. This mechanism is well disposed to parallelisation. The machine has been evaluated theoretically and empirically.

Avoiding Conventional Overheads in Parallel Logic Simulation: A New Architecture

Logic simulation is an important tool in VLSI design. The size of current VLSI circuits is increasing dramatically the computational effort demanded of this design tool. Parallel Processing techniques have reduced computational time. While processing speed is a crucial factor, equally important is the range of delay models that the simulation can support. Unfortunately, some parallel methods limit the accuracy of the delay model. Other parallel methods can only achieve a modest speedup through the use of standard computational mechanisms such as Load balancing and Event-scheduling. Deadlock issues must be resolved in these systems. As the processor numbers increase these tasks grow to the detriment of processing performance. This paper introduces an Associative memory architecture for logic simulation, APPLES, which eliminates the need of conventional support tasks, attains high speedup performance and is capable of simulating complex delay models. The architecture has been implemented as a Verilog model and evaluated theoretically and on various ISCAS-85 benchmarks.

An IP-XACT Library extended with verification information for functionality-based component selection

SummaryIn the Electronic Design and Automation (EDA) industry a gap between design and productivity exists and is even expanding. Also, consumers demand fancy products and new features at a faster pace. Consequently, to fulfill these rigid design cycles companies are reusing Intellectual Property (IP) components provided by third-party suppliers instead of creating them anew. However, no common format exists amongst companies which complicates IP exchange and reuse. Moreover, verification information, if existing, is provided separate from the IP. This paper introduces a novel approach to enable IP exchange with added verification information and metadata. To represent IP the new IP-XACT format is extended. Our developed library is able to store the extended IP with all its resources. The novel component selection strategy uses this information to retrieve matching IP based on their functionality and achieves accurate results.

Specification and automated simulation-based verification of power requirements for system-on-chips

Todays advances in silicon integration density allow more and more functionality to fit into a system-on-chip (SoC). However, this has made power consumption the most critical design constraint for system-on-chips (SoCs). Power consumption especially affects portable devices as it influences battery lifetime. Moreover, specification, design and verification of System-on-Chips have become increasingly complex. In this work we present a novel methodology which supports specification and automates verification of power requirements through simulation and power estimation. We demonstrate our approach on an example SoC. Therefore, we specify power requirements for a higher class radio frequency identification (RFID) tag. Then we automatically generate test cases which allow to estimate the RFID tags power consumption. To verify the power requirements we apply the test cases to the system model in simulation.