Christophe Quindroit

Concurrent Linearization: The State of the Art for Modeling and Linearization of Multiband Power Amplifiers

With the explosive growth of the smartphone and tablet markets, wide bandwidth voice and data communication have become ubiquitous. Users expect to use their wireless portable phone/computing devices at any place and at any time. Furthermore, with the todays economy of scale, yesterdays high-performance devices are todays entry-model devices.

FPGA Implementation of Orthogonal 2D Digital Predistortion System for Concurrent Dual-Band Power Amplifiers Based on Time-Division Multiplexing

A concurrent dual-band digital predistortion (DPD) system is presented to compensate for the nonlinearity of the radio-frequency power amplifiers (PAs) driven by a concurrent dual-band signal. Recently, a closed-form orthogonal polynomial basis has been introduced showing stability improvement compared with the conventional polynomial. An experimental test bed employing a field-programmable gate array (FPGA) linked to two mixed-signal system boards has also been presented. Based on the FPGA, this paper focuses on the hardware implementation of the new concurrent dual-band orthogonal DPD forward path using time-division multiplexing. Performances are evaluated with an experimental test setup cascading 1-10 W peak PAs and a dual-band signal center frequency spaced by 310 MHz. The lower side band (LSB) and upper side band (USB) are centered at 1890 and at 2200 MHz, respectively. Two signal scenarios are presented combining alternatively 1-carrier wide-band code-division multiple access (WCDMA) and 10-MHz long-term evolution (LTE) signals to a 5-carrier WCDMA signal. Experimental results show that the proposed time-division-multiplexing implementation approach gives similar performance compared with the software implementation with half of the resources. Adjacent channel power ratios (ACPRs) are reduced below -50 dBc and normalized mean-square error (NMSE) close to -40 dB.

Asymmetric Doherty Power Amplifier Designed Using Model-Based Nonlinear Embedding

A novel procedure is introduced for designing Doherty amplifiers using the model-based nonlinear-embedding technique. First, the Doherty intrinsic load-matching network is designed at the transistor current-source reference plane with the main and auxiliary devices interconnected. Identical devices with different biasing are used for realizing an asymmetric Doherty implementation with 9-dB back-off. The required multiharmonic impedances at the package planes are then obtained using the embedding device model for both devices, and the complex load impedance at the fundamental is projected back to resistive loads using an offset line. An even-number multisection impedance transformer and a reduced drain voltage of the main amplifier are used to design the asymmetric Doherty load network while providing the necessary loads to the main and auxiliary devices. The optimization of the drain efficiency and gain curves of the asymmetric Doherty operation for the proposed design is further investigated by adjusting the auxiliary gate-bias. An efficiency above 50% over an 11-dB power range is experimentally observed with 41.8-dBm peak output power using continuous wave (CW) at 2 GHz. Using a dual-input implementation of the designed Doherty power amplifier (PA), a systematic dual-input CW characterization of the Doherty operation is performed to establish the relative auxiliary-to-main phase offsets and power offsets yielding a maximum efficiency under constant gain. From this dual-input characterization, it is found that the optimal gate bias for single-input Doherty operation is the one for which the constant-gain maximum efficiency is achieved for a quasi-constant auxiliary-to-main input power ratio corresponding to the one implemented in the input divider in the single-input Doherty PA.

Concurrent dual-band digital predistortion for power amplifier based on orthogonal polynomials

This paper presents a 2D digital predistortion system to compensate for the nonlinearity of the power amplifier driven by a concurrent dual-band signal. In order to improve the numerical stability of the system, we introduce a new orthogonal polynomial basis. The numerical stability of the new representation is compared to the conventional polynomial. An experimental test bench employing an FPGA linked to two mixed signal system boards is also presented. Performances are evaluated with an experimental test setup using a 10W peak power amplifier and a dual-band signal (single-carrier WCDMA and 3-carrier WCDMA) center frequency spaced by 310MHz. Experimental results show numerical stability improvement with the new 2D orthogonal basis.

Efficient Least-Squares 2-D-Cubic Spline for Concurrent Dual-Band Systems

This paper presents and compares two types of 2-D cubic-spline (2-D-CS) digital predistorters for linearizing a power amplifier (PA), which is used in dual-band transmitters. In the conventional 2-D-CS representation, the gain functions must be first extracted using an alternate basis, whereas in the proposed 2-D least-squares cubic-spline (2-D-LSCS) approach, a new 2-D-CS basis is introduced such that the basis weights can be extracted directly from the measured data using the least-squares method. The 2-D basis functions are calculated from 1-D basis functions to reduce the signal-processing resource usage in the real-time implementation. A field-programmable gate-array (FPGA) test bench integrating the concurrent dual-band RF system is utilized to verify the linearization performance of the new 2-D-LSCS predistorter. Two different test scenarios involving three carrier-wideband code division multiple access and long-term evolution signals, which are 310 MHz apart, are considered. The experimental results on a 10-W dual-band PA shows that the proposed 2-D-LSCS basis improves the performance up to 3 dB in both the adjacent channel power ratio and normalized mean square error with reduced FPGA resources and faster extraction time when compared to the conventional 2-D memory-polynomial and 2-D-CS approaches.

2D cubic spline implementation for concurrent dual-band system

This paper presents a 2D cubic-spline (2D C-spline) implementation of digital predistortion (DPD) for the linearization of power amplifier (PA) used in dual band transmitters. The implementation uses a 2D look up table (2D-LUT) for storing the coefficients of the 2D C-spline. The transmitted signals are assumed to be sufficiently spaced wide apart so that only the in-band distortion in both the channels need to be accounted for. The frequency selective technique is used to implement the DPD in each band as it reduces the sampling frequency requirement for the analog to digital converters (ADC) and digital to analog converters (DAC) used in the transmit and feedback paths. An FPGA testbench integrating the concurrent dual band RF system is utilized to verify the linearization performance of the 2D C-spline predistorter. The linearization of two wideband code division multiple access (WCDMA) signals which are 310 MHz apart is investigated. The experimental results shows that the intermodulation distortion products are reduced by 25 dBc for a 10 W dual-band PA.

Adjustable Load-Modulation Asymmetric Doherty Amplifier Design Using Nonlinear Embedding

We developed a new asymmetric Doherty load modulation matching network using identical transistors for the main and auxiliary amplifiers. Asymmetric Doherty power amplifiers (PA) require a larger size transistor for the auxiliary PA than for the main PA to provide the higher power and wider load modulation range. Additional impedance transformers are introduced to alleviate this requirement when using identical devices. The drain bias voltage of the main amplifier is also reduced to achieve a wider back-off. Furthermore, a large-signal model-based nonlinear embedding method is applied to predict the input and output harmonic terminations, removing the need for the multi-harmonic source/load pull characterization. An asymmetric Doherty amplifier was built using two 15 W peak power packaged GaN transistors of the same size. 71 % drain efficiency at the peak power of 41.8 dBm and 62.7 % at the second peak of 32.8 dBm (9 dB back-off) were observed. Above 50% drain efficiency was maintained over an 11 dB power range. 51.86 % average drain efficiency was observed after linearization maintaining -51.46 dBc adjacent channel power ratio excited by 10 MHz bandwidth long term evolution signals with 9.96 dB peak to average power ratio.

Concurrent Dual-Band Modeling and Digital Predistortion in the Presence of Unfilterable Harmonic Signal Interference

Motivated by advanced-generation signals and corresponding trends for multiband, broadband, and ultra-wideband transmitters, several models have recently been proposed for digital predistortion in a dual-band concurrent transmission. These state-of-the-art models assume that two frequencies of operation are uncorrelated and harmonic products can be filtered out. However, when the harmonic of one signal falls on the frequency band of another signal, it cannot be removed with filters. This paper proposes a 3-D harmonic memory polynomial based model for the dual-band concurrent transmission in the presence of harmonic interferences. The model is extracted and predistortion is implemented using a low-cost field-programmable gate-array-based system including a transmitter and a feedback receiver. Using the proposed model, a performance improvement up to 22 dB in terms of normalized mean square error and performance improvement up to 20 dB in terms of the adjacent channel power ratio is achieved compared to a conventional dual-band memory polynomial model not including harmonics.

2D forward twin nonlinear two-box model for concurrent dual-band digital predistortion

In this paper, a dual-band forward twin nonlinear two-box model is proposed to compensate for the nonlinearity of the power amplifier in concurrent dual-band signal mode. By taking into account nonlinear memory effects, the new dual-band digital predistortion (DPD) architecture improves the linearization performances of the 2D-Hammerstein model while reducing the complexity compared to the 2D-DPD model. An experimental test bench based on an FPGA is also presented. Linearization and complexity performances are evaluated and compared using a 10W peak power amplifier and a dual-band signal (single-carrier LTE and 3-carrier WCDMA) center frequency spaced by 310MHz. Results show a reduced complexity while achieving similar performances as 2D-DPD. Adjacent channel power ratios (ACPRs) are reduced below -50 dBc and normalized mean square error (NMSE) close to -40 dB.

Quasi-exact inverse PA model for digital predistorter linearization

This paper reports the first experimental application of the recently reported quasi-exact inverse (QEI) for memory-polynomial or memory-spline models in the design of a digital predistorter (DPD) linearizing a power amplifier (PA). In comparison to indirect learning architecture, where the coefficients of the DPD are extracted by swapping the input and output variable in any PA model, the DPD extraction is performed from the PA model directly. One of the advantages of using this scheme is that the output noise of the PA is not included in the regression matrix, thus improving the performance. In this paper, B-splines are used to extract the PA model since the performance of the DPD depends on the accuracy of the PA model. The new DPD algorithm relies on an arbitrary number of memory delays as needed for the QEI of the PA model. The evaluation of the models performance is conducted on a real time application. A Long Term Evolution (LTE) signal of 10 MHz bandwidth is used to compare the performance with a memory polynomial (MP) DPD model used in indirect learning architecture. The measurement results demonstrate that there is a noticeable improvement in terms of Normalised Mean Square Error (NMSE) and Adjacent Channel Power Ratio(ACPR) when using the QEI model for DPD. Note that this is achieved without any iteration as in practical DPD systems. Better results are possible when the PA model represents the PA behavior more accurately.