Patrick Roblin

Frequency-Selective Predistortion Linearization of RF Power Amplifiers

This paper presents a frequency-selective RF vector predistortion linearization system for RF multicarrier power amplifiers (PAs) affected by strong differential memory effects. Differential memory effects can be revealed in two-tone experiment by the divergence for increasing tone-spacing of the vector Volterra coefficients associated with the lower and upper intermodulations tones. Using large-signal vector measurement with a large-signal network analyzer, a class-AB LDMOS RF PA is demonstrated to exhibit a strong differential memory effect for modulation bandwidth above 0.3 MHz. New frequency-selective RF and baseband predistortion linearization algorithms are proposed to separately address the linearization requirements of the interband and inband intermodulation products of both the lower and upper sidebands. Theoretical verification of the algorithms are demonstrated with Matlab simulations using a Volterra/Wiener PA model with memory effects. The baseband linearization algorithm is next implemented in a field-programmable gate array and experimentally investigated for the linearization of the class-AB LDMOS PA for two carrier wideband code-division multiple-access signals. The ability of the algorithm to selectively linearize the two interband and four inband intermodulation products is demonstrated. Adjacent channel leakage ratio of up to 45 dBc for inband and interband are demonstrated experimentally at twice the typical fractional bandwidth.

New Trends for the Nonlinear Measurement and Modeling of High-Power RF Transistors and Amplifiers With Memory Effects

Power amplifier (PA) behavior is inextricably linked to the characteristics of the transistors underlying the PA design. All transistors exhibit some degree of memory effects, which must therefore be taken into account in the modeling and design of these PAs. In this paper, we will present new trends for the characterization, device modeling, and behavioral modeling of power transistors and amplifiers with strong memory effects. First the impact of thermal and electrical memory effects upon the performance of a transistor will be revealed by comparing continuous wave and pulsed RF large-signal measurements. Pulsed-RF load-pull from the proper hot bias condition yields a more realistic representation of the peak power response of transistors excited with modulated signals with high peak-to-average power ratio. Next, an advanced device modeling method based on large-signal data from a modern nonlinear vector network analyzer instrument, coupled with modeling approaches based on advanced artificial neural network technology, will be presented. This approach enables the generation of accurate and robust time-domain nonlinear simulation models of modern transistors that exhibit significant memory effects. Finally an extension of the X-parameter (X-parameter is a trademark of Agilent Technologies Inc.) behavioral model to account for model memory effects of RF and microwave components will be presented. The approach can be used to model hard nonlinear behavior and long-term memory effects and is valid for all possible modulation formats for all possible peak-to-average ratios and for a wide range of modulation bandwidths. Both the device and behavioral models have been validated by measurements and are implemented in a commercial nonlinear circuit simulator.

A Generalized Architecture for the Frequency- Selective Digital Predistortion Linearization Technique

This paper presents a new architecture for the frequency-selective digital predistortion (DPD) for two- and three-band power amplifier (PA) linearization. Also, largely spaced-signal DPD using a digital intermediate frequency (IF) technique is demonstrated. The algorithm used accounts for differential memory effects up to fifth order for bands that can be arbitrarily spaced. The simulation and experimental studies are performed using various signal sets; two- and three-band multitone signals with various tone spacing, band separation, and complementary cumulative distribution function. An improvement of 10 dB over third-order linearization is demonstrated in simulation for more than 20 dB of adjacent channel power ratio reduction. The test signal and the linearization algorithm were implemented on a field-programmable gate array. The linearization algorithm was applied to an RF amplifier at 700-900 MHz. For the two-band case, more than 15 dB on the in-band, 13 dB on the third, and 5 dB on the fifth intermodulation distortion (IMD) cancellation were achieved. For the three-band case, more than 12 dB of IMD cancellation was observed. For largely spaced signal DPD, more than 15 dB of IMD cancellation was achieved. In the three-band case, the linearization of intermodulation byproducts overlapping with the in-band distortion is found to be of critical importance.

Analysis of MODFET microwave characteristics

A new ac MODFET model including distributed effects is presented. We have solved the wave equation of the MODFET, which automatically accounts for the propagation delay, capacitances, and charging resistances. Using a frequency power series proposed by Ziel, we derive an approximate analytic expression for the four intrinsic Y parameters. We verify that the truncated frequency power expansion used is accurate for frequencies up to twice the unilateral power-gain cutoff-frequency. The Y parameters derived hold from the threshold region to the edge of saturation. The theory was used to reproduce the dc characteristics of a 1-μm GaAlAs/GaAs MODFET together with its microwave characteristics measured from 2 to 18.4 GHz. Device parameters so obtained by fitting the I-V characteristics were used to calculate the MODFET Y parameters. They yield a closer fit to the data than the Y parameters obtained from conventional equivalent-circuit models. A reasonable prediction of the scattering parameters measured from 2 to 18.4 GHz is achieved with those device parameters. Further improvements can be obtained by optimizing the parasitics.

Simulation of hot-electron trapping and aging of nMOSFETs

An analysis of the degradation of 1- mu m-gate-length nMOSFET operating under normal biasing conditions at room temperature is reported. A physical model of hot-electron trapping in SiO/sub 2/ is developed and is used with a two-dimensional device simulator (PISCES) to simulate the aging of the device under normal biasing conditions. The initial degradation takes place near the high-field drain region and spreads over a long time toward the source. The degraded I-V characteristics of the MOSFET exhibit a shift of the pinchoff voltage and a compression of the transconductance, for forward and reverse operation, respectively. The simulated degradation qualitatively agrees with reported experimental data. Large shifts of the MOSFET threshold voltage for small drain voltages result as the degradation is spreading toward the source. An inflection point arises for low gate and drain voltages in the drain I-V characteristics of the MOSFET. This inflection point originates when the pinchoff of the channel-induced trapped-electron charge is overcome by the drain voltage; the drain acts as a second gate (short-channel effect). The estimation of the devices lifetime by simulated aging is proposed. >

Concurrent Linearization: The State of the Art for Modeling and Linearization of Multiband Power Amplifiers

With the explosive growth of the smartphone and tablet markets, wide bandwidth voice and data communication have become ubiquitous. Users expect to use their wireless portable phone/computing devices at any place and at any time. Furthermore, with the todays economy of scale, yesterdays high-performance devices are todays entry-model devices.

Nonlinear parasitics in MODFETs and MODFET I-V characteristics

A large-signal analysis of the source and drain resistance of MODFETs is reported. Velocity saturation in the two-dimensional electron gas (2DEG) and hypothetical rectifying effects in the n/sup +/-AlGaAs-i-GaAs interface are accounted for. Rectifying effects are found to be either absent or negligible. Current limitations in the 2DEG lead to the observed compression of the transconductance at large gate voltages, and an improved fit of the MODFET I-V characteristics is demonstrated using an approximate analytic formulation of the current-limited parasitic resistance. The high-frequency dependence of the source and drain resistance is also reported. A decrease of the source impedance for frequencies increasing from 1-30 GHz is predicted and can reach 30%, depending on the device structure. Such a frequency decrease of the parasitics is consistent with the reported increase of the effective transconductance of MODFETs at microwave frequencies. The reported frequency and current-limited parasitic models rely on parameters that can either be measured or calculated and are therefore appropriate for CAD applications. >

Model-Based Nonlinear Embedding for Power-Amplifier Design

A fully model-based nonlinear embedding device model including low- and high-frequency dispersion effects is implemented for the Angelov device model and successfully demonstrated for load modulation power-amplifier (PA) applications. Using this nonlinear embedding device model, any desired PA mode of operation at the current source plane can be projected to the external reference planes to synthesize the required multi-harmonic source and load terminations. A 2-D identification of the intrinsic PA operation modes is performed first at the current source reference planes. For intrinsic modes defined without lossy parasitics, most of the required source impedance terminations will exhibit a substantial negative resistance after projection to the external reference planes. These terminations can then be implemented by active harmonic injection at the input. It is verified experimentally for a 15-W GaN HEMT class-AB mode that, using the second harmonic injection synthesized by the embedding device model at the input, yields an improved drain efficiency of up to 5% in agreement with the simulation. A figure-of-merit is also introduced to evaluate the efficacy of the nonlinear embedding PA design methodology in achieving the targeted intrinsic mode operation given the model accuracy.

FPGA Implementation of Orthogonal 2D Digital Predistortion System for Concurrent Dual-Band Power Amplifiers Based on Time-Division Multiplexing

A concurrent dual-band digital predistortion (DPD) system is presented to compensate for the nonlinearity of the radio-frequency power amplifiers (PAs) driven by a concurrent dual-band signal. Recently, a closed-form orthogonal polynomial basis has been introduced showing stability improvement compared with the conventional polynomial. An experimental test bed employing a field-programmable gate array (FPGA) linked to two mixed-signal system boards has also been presented. Based on the FPGA, this paper focuses on the hardware implementation of the new concurrent dual-band orthogonal DPD forward path using time-division multiplexing. Performances are evaluated with an experimental test setup cascading 1-10 W peak PAs and a dual-band signal center frequency spaced by 310 MHz. The lower side band (LSB) and upper side band (USB) are centered at 1890 and at 2200 MHz, respectively. Two signal scenarios are presented combining alternatively 1-carrier wide-band code-division multiple access (WCDMA) and 10-MHz long-term evolution (LTE) signals to a 5-carrier WCDMA signal. Experimental results show that the proposed time-division-multiplexing implementation approach gives similar performance compared with the software implementation with half of the resources. Adjacent channel power ratios (ACPRs) are reduced below -50 dBc and normalized mean-square error (NMSE) close to -40 dB.

An Analytic Circuit-Based Model for White and Flicker Phase Noise in LC Oscillators

A general circuit-based model of LC oscillator phase noise applicable to both white noise and 1/f noise is presented. Using the Kurokawa theory, differential equations governing the relationship between amplitude and phase noise at the tank are derived and solved. Closed form equations are obtained for the IEEE oscillator phase noise for both white and 1/f noise. These solutions introduce new parameters which take into account the correlation between the amplitude noise and phase noise and link them to the oscillator circuit operating point. These relations are then used to obtain the final expression for voltage noise power density across the output oscillator terminals assuming the noise can be modeled by stationary Gaussian processes. For white noise, general conditions under which the phase noise relaxes to closed-form Lorentzian spectra are derived for two practical limiting cases. Further, the buffer noise in oscillators is examined. The forward contribution of the buffer to the white noise floor for large offset frequency is expressed in terms of the buffer noise parameters. The backward contribution of the buffer to the 1/Delta f2 oscillator noise is also quantified. To model flicker noise, the Kurokawa theory is extended by modeling each 1 /f noise perturbation in the oscillator as a small-signal dc perturbation of the oscillator operating point. A trap-level model of flicker noise is used for the analysis. Conditions under which the resulting flicker noise relaxes to an 1/Delta f3 phase noise distribution are derived. The proposed model is then applied to a practical differential oscillator. A novel method of analysis, splitting the noise contribution of the various transistors into modes is introduced to calculate the Kurokawa noise parameters. The modes that contribute the most to white noise and flicker noise are identified. Further, the tail noise contribution is analyzed and shown to be mostly up-converted noise. The combined white and flicker noise model exhibits the presence of a number of corner frequencies whose values depend upon the relative strengths of the various noise components. The proposed model is compared with a popular harmonic balance simulator and a reasonable agreement is obtained in the respective range of validity of the simulator and theory. The analytical theory presented which relies on measurable circuit parameters provides valuable insight for oscillator performance optimization as is discussed in the paper.