Christopher A. Ryan

Multiple fault simulation with random and clustered fault injection

A logic and fault simulator is described which provides gate-level multiple stuck-at fault simulation as well as traditional single stuck-at fault simulation. The multiple fault simulation supports random and clustered fault injection for the verification and evaluation of multiple fault detection capabilities of test vector sets as well as fault and defect-tolerant design techniques.

On parallel switch level fault simulation

Presents a novel switch level extension to parallel fault simulation and the switch level circuit partitioning needed for parallel processing. Using 9-valued logic, reverse level ordering and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<<ETX>>

9-valued 2-dimensional parallel switch level fault simulation

Switch level fault simulation increases accuracy over gate level fault simulation at the cost of increased complexity. A two-dimensional extension to parallel fault simulation for the switch level is presented. Using 9-valued logic and a parallel hardware accelerated fault simulator, simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input.<<ETX>>

Bridging fault simulation using Iddq, logic, and delay testing

Accepted integrated circuit verification techniques involve stuck-at fault simulation. However, it has been shown that the majority of actual physical faults in the faulty integrated circuit are bridging faults. For this reason, the interest in bridging fault simulation techniques have increase. One characteristic with bridging faults is that the bridging fault may have electrical as well as logical behavior. This characteristic makes detection of bridging faults more difficult and this characteristic increases the complexity of bridging fault simulation. The three techniques most widely used for bridging fault simulation are current testing, stuck-at testing, and delay testing. This paper compares the complexity and robustness of the three techniques and new developments in the three techniques. Results show the current testing technique to be the most robust and have the lowest complexity which approaches stuck-at fault simulation complexity.

FX: a fast approximate fault simulator for the switch-level using VHDL

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel nine-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the lines distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

Parallel Switch-Level Fault Simulation Performance Modeling using VHDL

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model the physical failures found in the integrated circuit. However, existing fault simulation techniques have a worst-case computational complexity of O(n 2), where n is the number of devices in the circuit. A Parallel Hardware Accelerated Fault Simulator (PHAFS) has been proposed in order to reduce fault simulation complexity to O(L2), where L is the number of levels of switches encountered when traversing the circuit from output to input. This paper presents the VHSIC (Very High Speed Integrated Circuit) hardware description language simulation techniques used to verify the parallel fault simulation algorithm and to verify the algorithms complexity. This paper also presents predicted speed-up performance results versus partition size for benchnark circuits.

An algorithm for parallel hardware accelerated switch level fault simulation

The complexity and large simulation time for switch level fault simulation has been addressed by performing two-dimensional parallel fault simulation using a parallel hardware accelerated fault simulator (PHAFS). The authors present an algorithm and complexity measure for parallel fault simulation as extended to the switch level. Using nine-valued logic, reverse level ordering, and the PHAFS, the switch level fault simulation complexity is reduced to O(L**2), where L is the number of levels of switches encountered when traversing from output to input. This computational complexity is far less than that of traditional methods, since it is polynomial with respect to the number of reverse levels in the circuit as opposed to the number of devices in the circuit.<<ETX>>

Circuit partitioning for distributed VHDL fault simulation

Switch-level faults, as opposed to traditional gate-level faults can more accurately model physical failures found on an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing distributed switch-level fault simulation using a novel switch-level circuit partitioning technique. Transistor reverse level order circuit partitioning is shown to produce groups of transistors that share fan-in at nodes. Using this partitioning technique, results show that distributed switch-level fault simulation achieves increased speed-up over distributed switch-level fault simulation using random fault set partitioning techniques.

Compiled-code VHDL approximate fault simulation

Switch-level faults, as opposed to traditional gate-level faults, can more accurately model physical failures found in an integrated circuit. However, one problem with switch-level fault simulation is that of long simulation times. This paper addresses this problem by performing fast approximate switch-level fault simulation using transistor reverse level ordering, and a novel 9-valued switch-level extension to observability. The probability of propagation of a fault from an arbitrary line of the switch-level circuit to the primary output is shown to be a function of the average node fan-in and the lines distance to primary output. Using this probability, results show one order of magnitude of complexity speed-up as compared to traditional fault simulation techniques, while maintaining good accuracy.

On the complexity of bridging fault simulation techniques for CMOS integrated circuits

Accepted integrated circuit verification techniques involve stuck-at fault simulation. However, it has been shown that the majority of actual physical faults in the faulty integrated circuit are bridging faults. For this reason, the interest in bridging fault simulation techniques has increased. One characteristic with bridging faults is that the bridging fault may have electrical as well as logical behavior. This characteristic makes detection of bridging faults more difficult and this characteristic increases the complexity of bridging fault simulation. The three techniques most widely used for bridging fault simulation are current testing, stuck-at testing and delay testing. This paper compares the complexity and robustness of the three techniques and new developments in the three techniques. Results show the current testing technique to be the most robust and have the lowest complexity which approaches that of stuck-at fault simulation complexity.