Christopher J. Waskiewicz

EUV lithography at the 22nm technology node

We are evaluating the readiness of extreme ultraviolet (EUV) lithography for insertion into production at the 15 nm technology node by integrating it into standard semiconductor process flows because we believe that device integration exercises provide the truest test of technology readiness and, at the same time, highlight the remaining critical issues. In this paper, we describe the use of EUV lithography with the 0.25 NA Alpha Demo Tool (ADT) to pattern the contact and first interconnect levels of a large (~24 mm x 32 mm) 22 nm node test chip using EUV masks with state-of-the-art defectivity (~0.3 defects/cm2). We have found that: 1) the quality of EUVL printing at the 22 nm node is considerably higher than the printing produced with 193 nm immersion lithography; 2) printing at the 22 nm node with EUV lithography results in higher yield than double exposure double-etch 193i lithography; and 3) EUV lithography with the 0.25 NA ADT is capable of supporting some early device development work at the 15 nm technology node.

56 nm pitch copper dual-damascene interconnects with triple pitch split metal and double pitch split via

This work demonstrates the building of a 56 nm pitch copper dual damascene interconnects which connects to the local interconnect level. This M1/V0 dual-damascene used a triple pitch split bi-directional M1 and a double pitch split contact (V0) scheme where the local interconnects are with double pitch split in each direction, respectively. This scheme will provide great design flexibility for the advanced logic circuits. The patterning scheme is multiple negative tone development lithography-etch. A memorization layer is utilized in the triple patterned M1 and the double patterned V0 levels, respectively. After transferring the two via levels into the metal memorization layer, a self-aligned-via (SAV) RIE scheme was used to create vias confined by line trenches such that via to line spacing is maximized for better reliability. Seven litho/etch steps (LIP1/LIP2/V0C1/V0C2/M1P1/M1P2/M1P3) were employed to present this revolutionary interconnects.

Spacer-defined double patterning for 20nm and beyond logic BEOL technology

Spacer-defined double patterning was investigated as a patterning option for 20/14-nm logic technologys back-end-of-line (BEOL), and compared with the double patterning options of front-end-of-line (FEOL). Negative spacer-defined double patterning was used to provide less overlay impact and variable CD control on the metal lines compared with other double patterning techniques. Block lithography as a 2nd exposure was able to maintain better tip-to-tip and tip-to-line fidelity by forming lines that behave as a additive etch block. SiO2 spacer was directly deposited on resist core-mandrel via a low-temperature deposition process. Resist integrity was optimized through aerial image and mask optimization as well as resist selection processes. Design decomposition of the BEOL layout was identified as a major challenge in enabling the spacer-defined double patterning. Finally, successful integration of the patterning into the BEOL device was demonstrated.

56nm-pitch low-k/Cu dual-damascene interconnects integration with sidewall image transfer (SIT) patterning scheme

Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel SIT process for 56nm-pitch Cu line is investigated to develop the constant line pitch and less line edge roughness (LER). The basic electrical properties such as line open/short and via chain open/short yields are ~100%. The 56nm-pitch R-C variation is comparable to simulated 80nm-pitch R-C variation. The SIT patterning process is a strong candidate to improve the R-C variation for sub50nm-pitch technology nodes.