Tyson S. Hall

An introductory digital design course using a low-cost autonomous robot

This paper describes a new digital design laboratory developed for undergraduate students in this electrical and computer engineering curriculum. A top-down rapid prototyping approach with commercial computer-aided design tools and field-programmable logic devices (FPLDs) is used for laboratory projects. Students begin with traditional transistor-transistor logic-based projects containing a few gates and progress to designing a simple 16-bit computer, using very high-speed integrated circuits hardware description language (VHDL) synthesis tools and an FPLD. To help motivate students, the simple computer design is programmed to control a small autonomous robot with two servo drive motors and several sensors. The laboratory concludes with a team-based design project using the robot.

Automatic rapid programming of large arrays of floating-gate elements

The use of floating-gate elements on analog circuits has increased over the last few years. Floating-gate transistors are been used for analog multiplication, memory storage, on-chip bias, offset removals, etc. Complex systems, such as imagers and filter arrays, use thousands to millions of programmable floating-gate elements. The programming speed and precision of these elements plays a major role on the performance of these systems. In this paper we present a system approach that allows for automatic rapid programming of large arrays of floating-gates. We achieve this by optimizing all the time consuming tasks involved in the programming, such as current measurements and drain pulsing among others.

Field-Programmable Analog Arrays: A Floating-Gate Approach

Floating-gate analog circuits are being used to implement advanced signal processing functions and are very useful for processing analog signals prior to analog to digital conversion. We present an architecture analogous to FPGA architectures for rapid prototyping of analog signal processing systems. These systems go beyond simple programmable amplifiers and filters to include programmable and adaptive filters, multipliers, gains, winner-take-all circuits, and matrix-array signal operations. We discuss architecture as well as details such as switching characteristics and interfacing to digital circuits or FPGAs.

Application performance of elements in a floating-gate FPAA

Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. In this paper, we explore the use of floating-gate devices as the core programmable element in a signal processing FPAA. A generic FPAA architecture is presented that offers increased functionality and flexibility in realizing analog systems. In addition, the computational analog elements are shown to be widely and accurately programmable while remaining small in area.

Developing large-scale field-programmable analog arrays

Summary form only given. Field-programmable analog arrays (FPAAs) provide a method for rapidly prototyping analog systems. Currently available commercial and academic FPAAs are typically based on operational amplifiers (or other similar analog primitives) with only a few computational elements per chip. While their specific architectures vary, their small sizes and often restrictive interconnect designs leave current FPAAs limited in functionality, flexibility, and usefulness. We explore the use of floating-gate devices as the core programmable element in a large-scale FPAA with applications in signal processing emphasized. An FPAA architecture is presented that offers increased functionality and flexibility in realizing analog signal processing systems, and experimental data from a testbed FPAA is shown. In addition, mainstream signal processing systems are discussed that can be effectively implemented on large-scale reconfigurable analog devices thereby realizing dramatic savings in power over traditional digital solutions and improved time-to-market over traditional analog designs.

Engaging undergraduate students with robotic design projects

This paper describes our experiences developing robotics design projects for undergraduate students in our electrical and computer engineering curriculum at Georgia Tech. Several low-cost alternatives for developing robot-based design projects and designing the associated electronics and sensors to control them are included.

Mapping algorithm for large-scale field programmable analog array

Modern advances in reconfigurable analog technologies are allowing field-programmable analog arrays (FPAAs) to dramatically grow in size, flexibility, and usefulness. With these advances, analog circuits and systems can be programmable, reconfigurable, adaptive, implemented on standard CMOS to take advantage of scaled CMOS technology, and at a density comparable to digital memories. Our goal in this paper is to develop the first physical design automation toolset for floating-gate based FPAA with focus on minimization of parasitic effects on FPAA interconnect. We provide graph-based analog circuit and FPAA device modeling suitable for efficient mapping. Our FPAA clustering algorithm constructs Computational Analog Blocks (CAB) from analog circuit elements while improving the utilization of the device and reducing its impact on the total number of routing switches used. Experimental results demonstrate the effectiveness of our approach.

A RISC Design: Synthesis of the MIPS Processor Core

1 1.1 Design Entry using the Graphic Editor_______________________________________ 9 1.2 Compiling the Design ____________________________________________________ 16 1.3 Simulation of the Design __________________________________________________ 17 1.4 Testing Your Design on an FPGA Board ____________________________________ 18 1.5 Downloading Your Design to the DE1 Board _________________________________ 19 1.6 Downloading Your Design to the DE2 Board _________________________________ 22 1.7 Downloading Your Design to the UP3 Board _________________________________ 25 1.8 Downloading Your Design to the UP2 or UP1 Board __________________________ 27 1.9 The 10 Minute VHDL Entry Tutorial _______________________________________ 29 1.10 Compiling the VHDL Design ______________________________________________ 32 1.11 The 10 Minute Verilog Entry Tutorial ______________________________________ 34 1.12 Compiling the Verilog Design______________________________________________ 36 1.13 Timing Analysis _________________________________________________________ 38 1.14 The Floorplan Editor_____________________________________________________ 39 1.15 Symbols and Hierarchy___________________________________________________ 40 1.16 Functional Simulation ____________________________________________________ 41 1.17 Laboratory Exercises_____________________________________________________ 42 2 2.1 FPGA and External Hardware Features_____________________________________ 47 2.2 The FPGA Board’s Memory Features_______________________________________ 48 2.3 The FPGA Board’s I/O Features ___________________________________________ 49 2.4 Obtaining an FPGA Development Board and Cables __________________________ 53 3 Programmable Logic Technology______________________________ 56 3.1 CPLDs and FPGAs ______________________________________________________ 59 3.2 Altera MAX 7000S Architecture – A Product Term CPLD Device _______________ 60 R A P I D P R O T O T Y P I N G O F D I G I TA L S Y S T E M S S O P C E D I T I O N