Christopher R. Hatem

Origin and Control of OFF-State Leakage Current in GaN-on-Si Vertical Diodes

Conventional GaN vertical devices, though promising for high-power applications, need expensive GaN substrates. Recently, low-cost GaN-on-Si vertical diodes have been demonstrated for the first time. This paper presents a systematic study to understand and control the OFF-state leakage current in the GaN-on-Si vertical diodes. Various leakage sources were investigated and separated, including leakage through the bulk drift region, passivation layer, etch sidewall, and transition layers. To suppress the leakage along the etch sidewall, an advanced edge termination technology has been developed by combining plasma treatment, tetramethylammonium hydroxide wet etching, and ion implantation. With this advanced edge termination technology, an OFF-state leakage current similar to Si, SiC, and GaN lateral devices has been achieved in the GaN-on-Si vertical diodes with over 300 V breakdown voltage and 2.9-MV/cm peak electric field. The origin of the remaining OFF-state leakage current can be explained by a combination of electron tunneling at the p-GaN/drift-layer interface and carrier hopping between dislocation traps. The low leakage current achieved in these devices demonstrates the great potential of the GaN-on-Si vertical device as a new low-cost candidate for high-performance power electronics.

Maximizing electrical activation of ion-implanted Si in In0.53Ga0.47As

A relationship between the electrical activation of Si in ion-implanted In0.53Ga0.47As and material microstructure after ion implantation is demonstrated. By altering specimen temperature during ion implantation to control material microstructure, it is advanced that increasing sub-amorphizing damage (point defects) from Si+ implantation results in enhanced electrical activation of Si in In0.53Ga0.47As by providing a greater number of possible sites for substitutional incorporation of Si into the crystal lattice upon subsequent annealing.

Comparison of thermal annealing effects on electrical activation of MBE grown and ion implant Si-doped In0.53Ga0.47As

The effect of thermal annealing on the net donor concentration and diffusion of Si in In0.53Ga0.47As is compared for electrically active layers formed by ion implantation versus molecular beam epitaxy (MBE). Upon thermal treatment at temperatures of 700 °C or higher for 10 min, both ion implanted and growth-doped substrates converge to a common net donor solubility. These results indicate that while MBE doped substrates typically exhibit higher active concentrations relative to implanted substrates, the higher active Si concentrations from MBE growth are metastable and susceptible to deactivation upon subsequent thermal treatments after growth. Active Si doping concentrations in MBE doped material and ion-implanted materials are shown to converge toward a fixed net donor solubility limit of 1.4 × 1019 cm−3. Secondary ion mass spectroscopy of annealed samples indicates that the diffusivity of Si in MBE doped substrates is higher than those of ion implanted substrates presumably due to concentration-depende...

High Performance 400 °C p + /n Ge Junctions Using Cryogenic Boron Implantation

We report high performance Ge p⁺/n junctions using a single, cryogenic (-100 °C) boron ion implantation process. High activation>4 × 10²⁰ cm^-3 results in specific contact resistivity of 1.7 × 10^-8 Ω-cm² on p⁺-Ge, which is close to ITRS 15 nm specification (1 × 10^-8 Ω-cm²) and nearly 4.5× lower than the state of the art (8 × 10^-8 Ω-cm²). Cryogenic implantation is shown to enable solid-phase epitaxial regrowth and lower junction depth through amorphization of the surface Ge layer. These improvements in Ge p⁺/n junctions can pave the way for future high mobility Ge p-MOSFETs.

Enhanced Ge n + /p Junction Performance Using Cryogenic Phosphorus Implantation

In this paper, we present a detailed study of temperature-based ion implantation of phosphorus dopants in Ge for varying dose and anneal conditions through fabricated n+/p junctions and n-type MOSFETs (nMOSFETs). In comparison with room temperature (RT) (25 °C) and hot (400 °C) implantation, cryogenic (-100 °C) implantation with a dose of 2.2e15 cm-2 followed by a (400 °C) rapid thermal annealing leads to 1) lower junction leakage with higher activation energy and 2) lower sheet resistance with higher dopant activation and shallower junction depth. Gate-last Ge nMOSFETs fabricated using cryogenic implanted n+/p source/drain junction (2.2e15 cm-2) exhibit lower OFF-current (upto 5x) and higher ON-current compared with RT (25 °C) and hot (400 °C) implanted nMOSFETs. This paper demonstrates that cryogenic implantation (-100 °C) can enable high-performance Ge nMOSFETs by alleviating the problems of lower activation and high diffusion of phosphorus in Ge.

Concentration-dependent diffusion of ion-implanted silicon in In0.53Ga0.47As

In contrast to prior reports, evidence of concentration-dependent diffusion is reported for Si implanted In0.53Ga0.47As. The Fickian and concentration-dependent components of diffusivities were extracted using the Florida object oriented process and device simulator. The migration energy for silicon diffusion in In0.53Ga0.47As was calculated to be 2.4 and 1.5 eV for the Fickian and concentration dependent components of diffusion, respectively. A lack of change in diffusivities at given anneal temperatures suggest that transient-enhanced diffusion has not occurred. Due to these findings, silicon diffusion at high doping concentrations (>1 × 1020 cm−3) should be better characterized and understood for future complimentary metal-oxide semiconductor applications.

Ultra-shallow junction formation using flash annealing and advanced doping techniques

As the demand for ever shallower, highly active and abrupt junctions continues, it is important to look at both the doping and activation portions of junction formation as a unit process. Advanced doping is useless without annealing methods that limit diffusion and provide high levels of electrical activation and new annealing techniques cannot make the junctions shallower than the as-doped profiles. This work has looked at optimizing several types of advanced doping (Plasma Doping and beamline ion implantation of molecular dopants) and a flash lamp-based ms annealing approach. With this combination, very shallow, abrupt and low resistivity junctions can be formed. Careful characterization was used to ensure the accuracy of the sheet resistance and junction depth measurements.

Co-implantation of Al+, P+, and S+ with Si+ implants into In0.53Ga0.47As

Elevated temperature, nonamorphizing implants of Si+, and a second co-implant of either Al+, P+, or S+ at varying doses were performed into In0.53Ga0.47As to observe the effect that individual co-implant species had on the activation and diffusion of Si doping after postimplantation annealing. It was found that Al, P, and S co-implantation all resulted in a common activation limit of 1.7 × 1019 cm−3 for annealing treatments that resulted in Si profile motion. This is the same activation level observed for Si+ implants alone. The results of this work indicate that co-implantation of group V or VI species is an ineffective means for increasing donor activation of n-type dopants above 1.7 × 1019 cm−3 in InGaAs. The S+ co-implants did not show an additive effect in the total doping despite exhibiting significant activation when implanted alone. The observed n-type active carrier concentration limits appear to be the result of a crystalline thermodynamic limit rather than dopant specific limits.

Implantation and Diffusion of Silicon Marker Layers in In0.53Ga0.47As

Continued effort has been placed on maximizing activation while controlling the diffusion of silicon doping in InGaAs for present and future complementary metal-oxide semiconductor devices. In order to explore the diffusion and activation behavior, Si marker layers were grown in InGaAs on InP by molecular beam epitaxy. The nature of Si diffusion was explored using a series of isoelectronic implants to introduce excess point defects near the layer. It was observed that excess interstitials reduce the Si diffusion consistent with a vacancy-driven diffusion mechanism. A diffusion and activation model implemented in the Florida object oriented process simulator has been developed to predict silicon diffusion behavior over a variety of temperatures and times. Using current and previous experimental data and complimentary density functional theory results, the diffusion model employs the SiIII–VIII pair as the primary mechanism for silicon diffusion in InGaAs.

Lateral Ge Diffusion During Oxidation of Si/SiGe Fins

This Letter reports on the unusual diffusion behavior of Ge during oxidation of a multilayer Si/SiGe fin. It is observed that oxidation surprisingly results in the formation of vertically stacked Si nanowires encapsulated in defect free epitaxial strained SixGe1-x. High angle annular dark field scanning transmission electron microscopy (HAADF-STEM) shows that extremely enhanced diffusion of Ge occurs along the vertical Si/SiO2 oxidizing interface and is responsible for the encapsulation process. Further oxidation fully encapsulates the Si layers in defect free single crystal SixGe1-x (x up to 0.53), which results in Si nanowires with up to -2% strain. Atom probe tomography reconstructions demonstrate that the resultant nanowires run the length of the fin. We found that the oxidation temperature plays a significant role in the formation of the Si nanowires. In the process range of 800-900 °C, pure strained and rounded Si nanowires down to 2 nm in diameter can be fabricated. At lower temperatures, the Ge diffusion along the oxidizing Si/SiO2 interface is slow, and rounding of the nanowire does not occur, while at higher temperatures, the diffusivity of Ge into Si is sufficient to result in dilution of the pure Si nanowire with Ge. The use of highly selective etchants to remove the SiGe could provide a new pathway for the creation of highly controlled vertically stacked nanowires for gate all around transistors.