Benjamin Colombeau

Benefits of Damage Engineering for PMOS Junction Stability

As CMOS devices continue to shrink, the formation of ultra shallow junction (USJ) in the source/drain extension remains to be a key challenge requiring high dopant activation, shallow dopant profile and abrupt junctions. The next generations of sub nano‐CMOS devices impose a new set of challenges such as elimination of residual defects resulting in higher leakage, difficulty to control lateral diffusion, junction stability post anneal and junction formation in new materials. To address these challenges for advanced technological nodes beyond 32 nm, it is imperative to explore novel species and techniques. Molecular species such as Carborane (C2B10H12), a novel doping species and a promising alternative to monomer Boron is of considerable interest due to the performance boost for 22 nm low power and high performance devices. Also, to reduce residual defects, damage engineering methodologies have generated a lot of attention as it has demonstrated significant benefits in device performance. Varian proprieta...

FDSOI devices: A solution to achieve low junction leakage with low temperature processes (≤ 650°C)

In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.

Cryogenic ion implantation near amorphization threshold dose for halo/extension junction improvement in sub-30 nm device technologies

We report on junction advantages of cryogenic ion implantation with medium current implanters. We propose a methodical approach on maximizing cryogenic effects on junction characteristics near the amorphization threshold doses that are typically used for halo implants for sub-30 nm technologies. BF2+ implant at a dose of 8×1013cm−2 does not amorphize silicon at room temperature. When implanted at −100°C, it forms a 30 - 35 nm thick amorphous layer. The cryogenic BF2+ implant significantly reduces the depth of the boron distribution, both as-implanted and after anneals, which improves short channel rolloff characteristics. It also creates a shallower n+-p junction by steepening profiles of arsenic that is subsequently implanted in the surface region. We demonstrate effects of implant sequences, germanium preamorphization, indium and carbon co-implants for extension/halo process integration. When applied to sequences such as Ge+As+C+In+BF2+, the cryogenic implants at −100°C enable removal of Ge preamorphiza...

Improvement of Poly Profile in Sub 30 nm Device By Damage Engineering and Tilted Implantation Method

Conventionally, P31 out‐gassing of floating gate by succeeding thermal processes happens in NAND FLASH that use floating gate structure, and this P31 out gassing causes degradation of PDR and cell characteristics in sub‐30 nm device. Usually, there is a method to keep PDR of in‐situ doped poly‐Si by increasing the concentration of P31, but this method also causes cell characteristics degradation by trap charge of tunnel oxide.So, we used another method of ion implantation to control P31 out‐gassing concentration of floating gate by declining effective channel length. If we use methods of low energy and zero tilt implantation, P31 Trap by dopant channeling occurs in tunnel oxide. So, we evaluated methods of low energy and tilted implantation. But in this case, there were poly loss and bending, due to the physical collision damage of implantation.Therefore, we evaluated the effects of tilt change, direction and temperature control of ion implantation to minimize poly loss of floating gate.

Benefits of Zero Degree Single Wafer High Energy Implants for Advanced Semiconductor Device Fabrication

High energy well implants for retrograde well formation are usually tilted to avoid channeling. However, this can cause the well profile under the STI (Shallow Trench Isolation) to be skewed or asymmetric due to shadowing by the resist. This results in poor inter‐well isolation and increased leakage currents. This problem becomes more pronounced below 65 nm design rules. In this paper, using experimental data and TCAD simulations we demonstrate the improvement in inter‐well isolation and junction characteristics that can be achieved with true‐zero well implants. Finally, we briefly discuss the corresponding die shrinkage that can be expected.