Katsu Nakamura

A CMOS analog front-end chip-set for mega pixel camcorders

In modern CCD video camera systems, packaging and optical requirements constrain the CCD to be mounted close to the camera lens, often on a board separate from the main signal processing. In this configuration, the analog signal from the CCD must be driven across a flexible cable to the main board, where analog pre-processing is performed. In previous camera generations, the challenge was simply to integrate all of the analog functions onto a single CMOS chip compatible with low voltage supplies. This results in low-cost low-power system partitioning now widely used for consumer CCD camera systems. As consumer CCD sensors move toward higher resolution, however, this conventional integration has weaknesses. This paper shows a modified analog front-end integration for high-speed CCD interface to overcome the problems of conventional partitioning.

A CMOS front-end for CCD cameras

Most modern camcorders use digital processing exclusively in the signal path for better performance even though image information from the CCD and the signal recorded on the internal VTR are both in analog form. Before the signal can be digitized, however, extensive clamping and low-noise gain must be applied. Consumer pressure for small camcorder size and low power have lead to the development of a system in which all the functions previously residing on a bipolar chip have been incorporated on the same CMOS die with the ADC, including a CDS block, an amplifier with variable gain from 0 to 34 dB, a black-level correction loop, an input clamp and a voltage reference. An emitter follower buffer is traditionally used between the CCD and the rest of the system for line driving, but this is the only portion of the analog signal chain external to the chip.

A 4-channel 20-to300 Mpixel/s analog front-end with sampled thermal noise below kT/C for digital SLR cameras

We present a 4-channel analog front-end (AFE) designed specifically for multichannel sensors used in digital single-lens reflex (DSLR) cameras. Multichannel sensors have been adopted as a solution to the increasing requirements for higher throughput in imaging systems. Single-channel AFEs have been published [1–4]; however, there are drawbacks to using multiple discrete single-channel AFEs in a multichannel system. For example, column readout patterns are particularly sensitive to mismatch between AFE channels. Also, DSLR cameras support many different frame capture modes and read-out patterns, requiring clock rates from below 10MS/s to over 70MS/s, and previous AFEs have not been designed to operate over such a wide range. This paper describes several design techniques developed for the DSLR application, including adaptive power scaling, an integrated reference buffer, and a low-noise sampling technique with sampled thermal noise below kT/C.

A 14b 74MS/s CMOS AFE for True High-Definition Camcorders

A 14b 74MS/s CMOS AFE is designed for true high-definition camcorder applications. This is the first published AFE capable of high-definition sample rates. The AFE operates from a 1.8V supply, achieves 78dB peak SNR, 1.4V input range, and dissipates 70mW

A 3 V CMOS video acquisition channel

A complete video acquisition channel has been integrated in a 0.6 /spl mu/m double-poly CMOS process. The system includes a video clamp, AGC, S/H amplifier, and 10-bit ADC. The signal chain is fully differential, and achieves /spl plusmn/0.35 LSB DNL at 14.3 MS/s dissipating 90 mW from a 3 V supply. The active area is 2.85 sq mm.

F4: High-speed image sensor technologies

High speed imaging is one of the fastest growing semiconductor markets. Growth is currently driven by consumer and industrial applications such as HD video, slow motion play-back, machine vision, 3D range capture, and robotics. This forum will present chip architectures, circuits, and system-level solutions used in CCD and CMOS image sensors for high speed cameras. Technology topics include photon detection devices, pixel circuits and array readout circuits, A/D converters, image processing and interface circuits presented by world leading experts from industry and academia. The potential applications of this technology will be demonstrated by ultra high speed capture solutions for 3D range imaging and robotics. For advanced applications, techniques for outputing high-throughput pixel data using analog or digital interfaces are described. The forum will conclude with a panel discussion where the attendees have the opportunity to ask questions and to share their views, and this all-day forum encourages open information exchange. The targeted participants are circuit designers and concept engineers working on image sensor and camera system design.