Indira Nair

AVPGEN-A test generator for architecture verification

This paper describes a system (AVPGEN) for generating tests (called architecture verification programs or AVPs) to check the conformance of processor designs to the specified architecture. To generate effective tests, AVPGEN uses novel concepts like symbolic execution and constraint solving, along with various biasing techniques. Unlike many earlier systems that make biased random choices, AVPGEN often chooses intermediate or final values and then solves for initial values that can lead to the desired values. A language called SIGL (symbolic instruction graph language) is provided in AVPGEN for the user to specify templates with symbolic constraints. The combination of user-specified constraints and the biasing functions is used to focus the tests on conditions that are interesting in that they are likely to activate various kinds of bugs. The system has been used successfully to debug many S/390 processors and is an integral part of the design process for these processors. >

A small test generator for large designs

We report an automatic test pattern generator that can handle designs with one million gates or more on medium size workstations. Run times and success rates, i.e. the fraction of faults that are resolved, are comparable to or better than those reported previously in the literature. No preprocessing is required and the amount of memory needed is less than 100 bytes per gate. The low memory requirements and high performance have been achieved by working with a larger but simpler search space, by simplifying decision making and backtracking and by using only implication techniques that are fast and that require no preprocessing.

Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system

As high-level synthesis techniques gain acceptance among designers, it is important to be able to provide a robust system which can handle large designs in short execution times, producing high-quality results. Scheduling is one of the most complex tasks in high-level synthesis, and although many algorithms exist for solving the scheduling problem, it remains a main source of inefficiency by either not producing high-quality results, not taking into account realistic design requirements, or requiring unacceptable execution times. One of the main problems in scheduling is the dichotomy between control and data. Many algorithms to date have been able to provide scheduling solutions by looking only at either the data part or the control part of the design. This has been done in order to simplify the problem; however, it has resulted in many algorithms unable to handle efficiently large designs with complex control and data functionality. This paper presents algorithms for combining dataflow and control-flow techniques into a robust scheduling system. The main characteristics of this system are as follows: 1) it uses path-based techniques for efficient handling of control and mutual exclusiveness (for resource sharing), 2) it allows operation reordering and parallelism extraction within the context of path-based scheduling, 3) it contains a control partitioning algorithm for design space exploration as well as for reducing the number of control paths, and 4) it combines the above algorithms into an adaptive scheduling system which is capable of trading optimality for execution time on-the-fly. Results involving billions of paths are presented and analyzed.

Exploring power management in multi-core systems

Power dissipation has become a critical design metric in microprocessor-based system design. In a multi-core system, running multiple applications, power and performance can be dynamically traded off using an integrated power management (PM) unit. This PM unit monitors the performance and power of each core and dynamically adjusts the individual voltages and frequencies in order to maximize system performance under a given power budget (usually set by the operating system). This paper presents a performance and power analysis methodology, featuring a simulation model for multi-core systems that can be easily reconfigured for different scenarios and a PM infrastructure for the exploration and analysis of PM algorithms. Two algorithms have been implemented: one for discrete and one for continuous power modes based on non-linear programming. Extensive experiments are reported, illustrating the effect of power management both at the core and the chip level.

Early analysis tools for system-on-a-chip design

The paper describes the need for early analysis tools to enable developers of todays system-on-a-chip (SoC) designs to take advantage of pre-designed components, such as those found in the IBM Blue Logic® Library, and rapidly explore high-level design alternatives to meet their system requirements. We report on a new approach for developing high-level performance models for these SoC designs and outline how this performance analysis capability can be integrated into an overall environment for efficient SoC design.

Architectural verification of processors using symbolic instruction graphs

High performance processor designs use techniques such as pipelining, multiple execution units, register renaming, bypass paths, and branch prediction to meet their goals. These techniques make them susceptible to design errors that are triggered only when executing complex sequences of instructions. We introduce a language called SIGL for specifying symbolic instruction graphs (SIGs) that can be used as templates for such test cases. SIGL allows specification of constraints in a high level template from which many test cases can be generated, all targeting some specific characteristic of a processor design. SIGL has been used successfully to check the conformance of various industrial processor designs to their architectural specifications.<<ETX>>

SEAS: a system for early analysis of SoCs

Systems-on-chip (SoC) continue to be very complex to design and verify, despite extensive component reuse. Although reusable components are predesigned and preverified, when they are assembled in an SoC there is no guarantee that the whole system will behave as expected from a performance, cost and integration point of view. In many cases this is because of faulty early design decisions regarding the architecture, core selection, floorplanning, etc. This paper presents a system for early analysis of SoCs which helps designers make early decisions regarding performance, area, timing and power; and allows them to quickly evaluate cross-domain effects, such as the effect that an architectural decision may have on the performance and chip area.

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Transaction-Level models have emerged as an efficient way of modeling systems-on-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transaction-based power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

Performance modeling for early analysis of multi-core systems

Performance analysis of microprocessors is a critical step in defining the microarchitecture, prior to register-transfer-level (RTL) design. In complex chip multiprocessor systems, including multiple cores, caches and busses, this problem is compounded by complex performance interactions between cores, caches and interconnections, as well as by tight interdependencies between performance, power and physical characteristics of the design (i.e., floorplan). Although there are many point tools for the analysis of performance, or power, or floorplan of complex systems-on-chip (SoCs), there are surprisingly few works on an integrated tool that is capable of analyzing these various system characteristics simultaneously and allow the user to explore different design configurations and their effect on performance, power, size and thermal aspects. This paper describes an integrated tool for early analysis of performance, power, physical and thermal characteristics of multi-core systems. It includes cycle-accurate, transaction-level SystemC-based performance models of POWER processors and system components (i.e., caches, buses). Power models, for power computation, physical models for floorplanning and packaging models for thermal analysis are also included. The tool allows the user to build different systems by selecting components from a library and connecting them together in a visual environment. Using these models, users can simulate and dynamically analyze the performance, power and thermal aspects of multi-core systems.

Power management of multi-core chips: challenges and pitfalls

Modern processor systems are equipped with on-chip or on-board power controllers. In this paper, we examine the challenges and pitfalls in architecting such dynamic power management control systems. A key question that we pose is: How to ensure that such managed systems are “energy-secure” and how to pursue pre-silicon modeling to ensure such security? In other words, we address the robustness and security issues of such systems. We discuss new advances in energy-secure power management, starting with an assessment of potential vulnerabilities in systems that do not address such issues up front.