Chrystelle Lagahe-Blanchard

III-V/Si photonics by die-to-wafer bonding

Photonic integrated circuits offer the potential of realizing low-cost, compact optical functions. Silicon-on-insulator (SOI) is a promising material platform for this photonic integration, as one can rely on the massive electronics processing infrastructure to process the optical components. However, the integration of a Si laser is hampered by its indirect bandgap. Here, we present the integration of a direct bandgap III-V epitaxial layer on top of the SOI waveguide layer by means of a die-to-wafer bonding process in order to realize near-infrared laser emission on and coupled to SOI.

Investigation of a Sequential Three-Dimensional Process for Back-Illuminated CMOS Image Sensors With Miniaturized Pixels

A new 3-D CMOS image sensor architecture is presented as a potential candidate for submicrometer pixels. To overcome the scaling challenge related to miniaturized pixel design rules, far beyond traditional 3-D stacking alignment capabilities, a sequential construction is applied. This paper gives a technical overview of this 3-D scheme and validates a part of its building blocks. As a consequence of a sequential process, the thermal budget is limited to ensure bottom device immunity. Subsequently, high-quality SOI film transfer above the first layer by direct bonding and etch back is demonstrated. Finally, the low-temperature processing of HfO2/TiN fully depleted silicon-on-insulator readout transistors is detailed and evaluated from a low frequency noise point of view.

Smart Stacking™ and Smart Cut™ technologies for wafer level 3D integration

The wafer stacking technology for 3D integration requires high quality bonding interfaces with uniform bonding films. Two wafer level stacking technologies - Smart Stacking™ and Smart Cut™ - are developed to address the manufacturing challenges for improved process cost efficiency.