Fabrice Letertre

Silicon carbide on insulator formation by the Smart-Cut® process

Abstract For the first time silicon carbide on insulator structures (SiCOI) were achieved by the Smart-Cut® process. These structures were formed on polycrystalline SiC and on silicon substrates. The technological solutions used and the structures obtained are presented in this paper.

Compound Semiconductor Heterostructures by Smart Cut™: SiC On Insulator, QUASIC™ Substrates, InP and GaAs Heterostructures on Silicon

Large band gap semiconductors will find more and more applications in such important fields as power electronics, high temperature electronics or optoelectronics where traditional semiconductors are not suitable. Very important efforts have been made in the last decade on the development of wide band gap materials. It is crucial for any industrial development to produce large-size materials with good quality at a reasonable cost. Unfortunately crystal growth of these refractory materials is difficult. For example, SiC can only be obtained using very high temperature sublimation or CVD techniques.

New semiconductor hetero-substrates for high temperature applications using the Smart-Cut(R) technology

Use of thin monocrystalline semiconductor film transfer by Smart-Cut(R) technology is of great interest for new device technologies especially in the field of high temperature electronics. In this paper we give an overview of recent results on two kind of hetero-substrates obtained by this process: UNIBOND(R) SOI (Silicon On Insulator) substrates and substrates based on Silicon Carbide layer transfer. The latest progress on SOI wafer quality is highlighted. For SiC transfer, we describe the kinetics of SiC layer splitting, and the morphological and electrical characteristics of the SiC layers. We also show that SiC/Si/sub 3/N/sub 4//polycrystalline SiC structures can be fabricated using Smart-Cut technology. Polycrystalline SiC and silicon nitride have been chosen to replace the silicon substrate and silicon dioxide layers to make the overall structure compatible with very high temperature device processing and very harsh device environments.