Yih-Long Tseng

A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula

A ROM-less direct digital frequency synthesizer employing trigonometric quadruple angle formula is present in this paper. The worse case spectral purity is better than -130 dBc. The amplitude resolution is up to 13 bits, while the phase resolution is 12 bits. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is circumscribed and the resolution is preserved.

Wideband 70dB CMOS digital variable gain amplifier design for DVB-T receiver's AGC

This paper presents a novel VGA (variable gain amplifier) design which is applied in the AGC (automatic gain control) loop of DVB-T receivers. A total of three tunable gain stages are cascaded to provide a 70 dB dynamic range. Each gain stage is based on a DVGA (digital variable gain amplifier) which is composed of a plurality of GB (gain block) and a fully differential degeneration amplifier (FDDA). The GB are digitally controlled current mirrors which are used to determine the gain of the DVGA. A CMFB (common-mode feedback) circuitry is used to stabilize the FDDA. The bandwidth of the proposed design verified by HSPICE post-layout simulations is better than 95 MHz at every PVT corner which is sufficient for the DVB-T IF mixed-signal processing.

A 1.2 GHz programmable DLL-based frequency multiplier for wireless applications

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.

A 4-kB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.

Phase-Adjustable Pipelining ROM-Less Direct Digital Frequency Synthesizer With a 41.66-MHz Output Frequency

A high-speed phase-adjustable read-only-memory less direct digital frequency synthesizer employing trigonometric quadruple angle formula is presented. A ten-stage pipelining architecture is employed based upon decomposition of phase operands. Spectral purity is better than -130 dBc for the worst case spurious-free dynamic range. The resolution is up to 12 bits. Most importantly, the output sinusoidal frequency is higher than 40 MHz, which is far higher than the 32-MHz requirement of Korean personal communications system, global system for mobile communications, and Bluetooth. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is limited and the resolution is preserved

Low-power small-area digital I/O cell

A novel low-power and small-area digital I/O cell is proposed in this work. The new input/output (I/O) cell drastically reduces the I/O power consumption, which has been considered as the major power dissipation of the whole chip. The maximum operating clock is 500 MHz given a 10-pF offchip load. On top of the power saving feature, the proposed cell occupies merely 10535.2=4167.45 (transmitter)+6367.8 (receiver) /spl mu/m/sup 2/ which is far less than any prior commercially available I/O and low-voltage differential signaling I/O cells. Physical measurements of the proposed I/O cells show that the delays of the transmitter and the receiver are 1.1 and 1.8 ns, respectively. The largest power/bandwidth of the proposed design is 38.9 /spl mu/W/MHz when transmitting.

A temperature-insensitive self-recharging circuitry used in DRAMs

This paper presents a practical self-recharging circuitry for DRAMs. The proposed self-recharging circuitry not only reduces the standby power by monitoring the voltage drop caused by the data loss of a memory cell but also adjusts the recharging period of the memory cell that results from leakage currents. The proposed design is insensitive to temperature variations. A 1-Kb DRAM using our design is fabricated by a TSMC 0.35-/spl mu/m 1P4M CMOS process. The physical measurement of the proposed design on silicon verifies the correctness of the proposed circuitry.

Dual-polarity high voltage generator design for non-volatile memories

A novel voltage generator using 4 clocks with two different phases is presented in this work to provide a high voltage supply required by non-volatile memories during programming mode and erase mode operations. Both the positive and negative polarities of the voltage are generated to serve as the programming voltage and the erase voltage, respectively. The proposed design is carried out by gated pass transistors and switched capacitors. The regulated generated voltages which the proposed design can provide is +11.7 V and -11.6 V given VDD = 2.5 V when the circuit is implemented by TSMC 0.25 /spl mu/m 1P5M CMOS technology. The maximum power dissipation is estimated to be 3.8 mW given 12.5 MHz clocks.

Switched-current 3-bit CMOS wideband random signal generator

The paper presents a switched-current circuit implementation of a chaotic algorithm to generate a white noise. A 3-bit digital normalizer is utilized to adjust the coefficients in the piecewise-linear transfer function such that the probability of the generated numbers will be very close to a uniform distribution. A 1.0 GHz linear sample track-and-hold circuit is applied in the random number generator (RNG) to achieve the goal of a wide 4.0 MHz bandwidth. TSMC 0.25 /spl mu/m 1P5M CMOS process is used to carry out the proposed design. The operating clock is 10 MHz, while the measured bandwidth of the generated noise is 4 MHz.

High-PSR bias circuitry for NTSC sync separation

This paper presents a simple and bias generation circuitry (BGC) with temperature compensation. The proposed BGC utilizes step-down regulators and a bandgap-based bias with cascade current control. The clamping voltages required for sync separation from an NTSC signal are generated. Detailed PSR (power rejection ratio) analysis of the proposed BGC is also derived to circumscribe the clamping voltage variation. The worst variation of the proposed design verified by HSPICE post-layout simulations is 4.2% given a [-50/spl deg/C, +150/spl deg/C] temperature range, and a VDD(=5V) +10%.