Chuck Dennison

A floating gate based 3D NAND technology with CMOS under array

NAND Flash has followed Moores law of scaling for several generations. With the minimum half-pitch going below 20nm, transition to a 3D NAND cell is required to continue the scaling. This paper describes a floating gate based 3D NAND technology with superior cell characteristics relative to 2D NAND, and CMOS under array for high Gb/mm2 density.

Discontinuity of B‐diffusion profiles at the interface of polycrystalline Si and single crystal Si

Boron diffusion in polycrystalline Si‐on‐single crystal Si systems has been studied by secondary ion mass spectrometry. The extrapolated B‐diffusion profiles in polycrystalline Si and in the single crystal Si substrate reveal a discontinuity at the polycrystalline Si‐single crystal Si interface. The discontinuity in the B profiles is believed to occur due to the blockage of B‐defect complexes by the interfacial oxide between polycrystalline Si and the single‐crystal Si substrate, as well as the immobility of these defect complexes in single crystal Si. The B in the implant peak region above the B solid solubility limit is found to be immobile in single crystal Si during annealing due to the formation of electrically inactive B‐defect complexes. In polycrystalline Si, however, our results show that the B in the peak region spreads out more rapidly than in single crystal Si possibly due to the diffusion of B‐defect complexes along grain boundaries. The B‐defect complexes are electrically inactive as determi...

Development of polysilicon TFTs for 16 MB SRAMs and beyond

Summary form only given. The authors discuss the development and optimization of polysilicon grain microstructure, gate dielectric ,and light doped drain offset (LDO) for thin-film transistors (TFTs). The nominal TFTs used in this study had a W/L of 0.7/1.2 mu m with a drain offset of 0.3 mu m. Different gate dielectrics (SiO/sub 2/, NO, ONO) with thickness of 10-50 nm were evaluated. The results suggest that an LDO implant is essential for obtaining ON/OFF ratios greater than 10/sup 5/ while reducing the TFT sensitivity to drain-offset misalignment. The ONO dielectric is superior to NO stacks or oxide in terms of oxide leakage and ON/OFF ratios. A 3*10/sup 14/ Si implant after solid-phase crystallization (SPC) improves the slope by reducing the interface trap density. Therefore, significant performance enhancements in leakage ( 10/sup 6/) can be realized using LDO TFTs with stacked gates and an Si implant following SPC. >

A physically based phenomenological model using Boltzmann-Matano analysis for boron diffusion from polycrystalline Si into single crystal Si

The diffusion of boron in single crystal Si from a BF2-implanted polycrystalline Si film deposited on single crystal Si has been accurately modeled. The effective diffusivities of boron in the single crystal Si substrate have been extracted using Boltzmann-Matano analysis and the new phenomenological model for B diffusivity has been implemented in the PEPPER simulation program. The model has been implemented for a range of furnace anneal conditions (800 to 950°C, from 30 min to 6h) and implant conditions (BF2 doses varied from 5×1015 to 2×1016 cm−2 at 70 keV).

Oxide‐nitride storage dielectrics on smooth and rough polycrystalline silicon layers

We demonstrate that for the same capacitance value, 9.5‐nm‐thick oxide‐nitride storage dielectrics deposited on rough polycrystalline silicon exhibit a lower leakage current and a higher lifetime than 5.9 nm layers on smooth polycrystalline silicon. Leakage current reduction of more than two orders of magnitude and a lifetime increase of more than three orders of magnitude are reported. These improvements are explained by the nitride bulk‐limited type of conduction. Our data show that textured storage capacitors have all the properties required for efficient fabrication of 64 megabit dynamic random access memories.

Furnace N2O oxidation process for submicron MOSFET device applications

The mobility and reliability characteristics of submicron nMOSFETs with oxynitride gate dielectric of various oxide thicknesses (50, 80 and 120 A), and oxidation temperatures (907, 957 and 1057°C) grown in a conventional furnace have been investigated. Oxynitride gate devices show higher mobility than that of control oxide devices under high normal field. The oxynitride devices exhibit much less degradation (ΔGm/Gm and ΔVt) under channel hot-electron stress. Based on lifetime extrapolation, non-LDD MOSFETs using this new oxynitride dielectrics are predicted to have lifetime substantially longer than 10 years under 3.3 V operation.

Study of lateral non-uniformity as a function of junction depth in ultra-shallow junctions and its effect on leakage behavior in as-deposited polycrystalline Si and amorphous Si diodes

Abstract Heavily implanted polycrystalline Si films are finding increasing applications as solid diffusion sources, for example, in the formation of ultra-shallow junctions in elevated source/drain metal-oxide-semiconductor field effect transistors and polycrystalline Si emitter bipolar junction transistors. For these applications the dopants are implanted into the polycrystalline Si layer and subsequently diffused into the underlying Si substrate. The diffusion behavior, is however, determined by the evolution of the polycrystalline Si grain microstructure, A large final grain size could lead to laterally more non-uniform and hence leakier junctions. These non-uniformities are lesser for high thermal budget anneals (1100–1150°C, 30 s) than for lower thermal budget anneals (950°C, 30 s) because any doping inhomogeneities in the Si substrate get smeared out as the junction becomes deeper. The junction depth, however, cannot be increased indefinitely from a device viewpoint and a trade-off between leakage current and junction depth has to be made. In this paper, we will study the effect of grain microstructure of ion-implanted as-deposited amorphous Si and as-deposited polycrystalline Si diffusion sources on the diffusion of As and B in the Si substrate, correlate it to the electrical properties of the ultra-shallow junctions formed using this technique.

Analysis and modeling of submicron drain-offset polysilicon thin film transistors (TFTs)

Drain-offset polysilicon thin-film transistors (DO-TFTs) with different offset lengths and doping were fabricated and characterized. The grain boundary trap states in the offset region strongly influence the electrical behavior of the TFTs. The on state current is influenced by the grain microstructure in the drain-offset region and channel region, as evidenced by the drain current activation energy measurements. The off state leakage current is dominated by the generation of carriers in the drain offset depletion region, where the trap states serve as generation/recombination centers and reduce the barrier for tunneling. A model based on the Poole-Frenkel effect and thermionic field emission was developed to account for the leakage mechanism.