Surya Bhattacharya

Interconnect design and analysis for Through Silicon Interposers (TSIs)

The trend of increasing digital system performance by downscaling the device size poses daunting challenges in system design due to the increased power density, higher I/O count, interconnect bandwidth, and timing closure requirements. Silicon carrier with Through Silicon Vias (TSVs) or TSI technology is identified as a system and packaging level solution to overcome all those challenges. In this paper we describe the key electrical elements in a typical TSI digital system and discuss their impact on overall system performance. We also discuss the system level power integrity analysis for TSI as its power delivery is one of the major engineering challenges.

An Analytical Capacitance Model for Through-Silicon Vias in Floating Silicon Substrate

Through-silicon via (TSV) is an integral part of 2.5-D IC technology leveraged for multichip heterogeneous integration to achieve shorter interconnects, faster speed, and lower power consumption in the state-of-the-art circuit systems. These 2.5-D ICs use a silicon substrate, where there are no ground contacts unlike traditional 2-D ICs or 3-D ICs. TSVs in such electrically floating substrates call for new electrical models as well as improved parasitic extraction (PEX) methodology. Therefore, in this paper, an analytical capacitance model for TSVs in a 2.5-D IC is derived and validated. A TSV-to-TSV crosstalk expression is also validated and further extended to create an accurate 2.5-D IC PEX framework in addition to design robust grounding schemes, such that the TSV-to-TSV crosstalk coupling in an entire 2.5-D IC would be minimal even with floating silicon substrate. It is shown that a large number of regularly distributed power and ground TSVs provide an effective shield for the TSV-to-TSV crosstalk coupling and are highly recommended in the 2.5-D ICs.

Fabrication and Assembly of Cu-RDL-Based 2.5-D Low-Cost Through Silicon Interposer (LC–TSI)

Two-and-a-half-dimensional integration enables high-density interdie connections with low cost. This paper presents a through silicon interposer (TSI) fabrication process and detailed characterization and measurement results of redistribution layers and through silicon vias for low-cost 2.5-D integration.

2.5D through silicon interposer package fabrication by chip-on-wafer (CoW) approach

In this paper, the fabrication process and results of 2.5D through silicon interposer (TSI) package using polymer based RDL and chip-on-wafer (CoW) stacking-first approach is presented. The through silicon interposer is fabricated on a 300 mm silicon substrate with Cu filled vias of aspect ratio of 1:10. Fine-pitch Cu RDL using semi-additive process and polymer based dielectric is used to form the 3 layer of rerouting layer on front-side. Chips with micro-bumps are flip chip assembled onto the under bump metallization (UBM) of the 12 inch interposer substrate using thermal compression bonding via chip-on-wafer (CoW) format on the thick interposer substrate A wafer level molding process is used to form the over-mold encapulation over the assembled chips. The over-mold encapsulation is mechanically thinned down to reduce the warpage of the molded interposer and temporary bonded to a silicon carrier. Mechanical-grinding and chemical mechanical polishing (CMP) is used to expose the Cu vias from the backside. Cu-RDL process is used to form the backside re-routing layer and UBM for solder bumps. The completed interposer wafer is then diced into singulated packages for assembled to printed circuit board (PCB).

A cost model analysis comparing via-middle and via-last TSV processes

Cost remains a key factor for implementation of Through Silicon Via (TSV) in high-volume manufacturing. As compared to via-first and via-middle TSV, via-last (from wafer back-side) TSV possesses the advantage of a more simple process flow and more flexibility in integration for more varied applications. Previously, a cost model analysis for Through-Silicon-Interposer (TSI) using via-first TSV has been presented [1]. In this paper, we will apply a similar model to analyse and compare the fabrication cost for our current via-last and via-middle process flow. A CMP-based via-last process flow is used as a reference baseline in this study. This process flow follows that of a conventional via-middle TSV, but differs mainly in the absence of a TSV backside reveal process. Based on our analysis results, our baseline via-last TSV flow shows ~10% cost reduction when compared to via-middle TSV. We further explored an alternative via-last process flow (combining TSV and RDL into a single plating step) as reported in [2] for a further 10% reduction in cost.

Co-Design for Low Warpage and High Reliability in Advanced Package with TSV-Free Interposer (TFI)

TSV-Free Interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. Co-design modelling methodology is established for TFI technology with considering wafer process, package assembly and package/board level reliability and thermal performance to optimize structure design, wafer process, assembly process and material selection. Experimental results are used for validating warpage modelling results. Through wafer level modelling, suitable carrier wafer and EMC materials are recommended to control wafer warpage less than 2mm. Effects of package substrate coefficient of thermal expansion (CTE) and stiffener on assembly induced package warpage are simulated to reduce package warpage. The recommended materials and geometry design based on reliability are aligned with that from wafer and package warpage simulation results. The final test vehicle (TV) design and material selection are determined based on co-design modelling results for achieving successful TFI wafer process and package assembly process and long term package/board level reliability.

Study on Low Warpage and High Reliability for Large Package Using TSV-Free Interposer Technology Through SMART Codesign Modeling

Through-silicon via (TSV)-free interposer (TFI) technology eliminates TSV fabrication and reduces manufacturing and material cost. In this paper, structure–material–assembly–reliability–thermal (SMART) codesign modeling methodology is established for a package using TFI technology by considering wafer process, package assembly and package/board-level temperature cycling reliability, and thermal performance to optimize structure design, assembly process, and material selection. Experimental results are used to validate wafer warpage modeling results first. Through wafer-level modeling, suitable carrier and molding compound materials are recommended to control wafer warpage less than 2 mm for 12-in molded wafer. Effects of coefficient of thermal expansion of package substrate and stiffener on package warpage induced by assembly reflow process are simulated and analyzed. The recommended materials and geometry design based on thermal cycling reliability simulation are aligned with that from wafer and package warpage simulation results. The final test vehicle design and material selection are determined based on SMART codesign modeling results for achieving successful TFI wafer process and package assembly and long-term board-level reliability.

Heterogeneous system implementation using through-silicon interposer (TSI) technology

In this paper, we demonstrate a 2.5D/3D IC design methodology adopting 2D traditional IC design tools and show a FPGA-Memory system implementation for TSI. Post layout simulations at 533Mbps (266MHz) shows that the energy consumption of the FPGA-Memory channel is ~6pJ/bit over 20mm long RC interconnects.

60GHz wideband Yagi-Uda antenna integrated on 2.5D through silicon interposer

This paper proposes a 60 GHz wideband Yagi-Uda antenna for 2.5 Through Silicon Interposer (TSI) platform. The integrated antenna comprises two parts: a wideband Marchand balun and a differential Yagi-Uda antenna. Marchand balun transfers the balanced signals to un-balanced ones, and subsequently used to feed the differential Yagi-Uda antenna. To achieve wideband, the discussed Marchand balun is realized with the strong broadside coupling between metal layers based on redistributed layer (RDL) technology. Its insertion loss is 3.8 dB, and 15 dB return loss band is from 52 GHz to 74.3 GHz. Phase deviation is consistent and 1-20 from the ideal differential outputs. The proposed Yagi-Uda antenna constitutes a half-wavelength dipole as the antenna exciter; the ground plane of rear feeding network is inherently used as inductive reflector. In the front side, a 0.68-wavelength open-circuited stub functions not only as a capacitive director, but also introduces one more resonant mode to widen the antenna operating bandwidth. Lastly, impedance matching from exciter dipole and 100 Ω Marchand balun is realized by the co-planar strip (CPS) line. As a result, a wideband Yagi-Uda antenna on TSI platform with peak 4.7 dBi endfire radiation is successfully achieved, and its fractional bandwidth is 26.0% from 54 GHz to 70.2 GHz.

The cost study of 300mm through silicon interposer (TSI) with BEOL interconnect

The cost is always an important parameter for the new technical application. Through Si Via (TSV) technology becomes hot topic since image sensor application. We setup cost model according to our process flow and throughput for the cost study and reduction of 300mm TSI interposer. High cost area was calculated through the cost model. Full TSI process flow was separated as TSV, BEOL, Top UBM, TDDB, BSR, BS RDL& Bump sub-process flow. Top three high cost sub-process flow for 2.5D TSI with BEOL interconnect were identified from TSI process flow. Top three processes modules were isolated for each high cost subprocess flow. The high cost process modules were analyzed and explained in the paper. Two approaches were proposed for the cost reduction base on cost model analysis.