Chenhsin Lien

An Analytical Model of Short-Channel Effect for Metal–Oxide–Semiconductor Field-Effect Transistor with Insulated Shallow Extension

In this paper, we present an analytical short-channel threshold voltage model without any fitting parameter for the metal–oxide–semiconductor field-effect Transistor (MOSFET) with insulated shallow extension (ISE). Excellent agreements between the numerical simulated results and this model are obtained. Very good suppression of the short-channel effect is observed for this ISE MOSFET. Both the sidewall-oxide thickness and shallow-extension depth play a major role in containing the short-channel effect. The threshold-voltage equation is found by using the effective-doping model. The effective doping is derived from the knowledge of the channel potential. The channel potential is obtained by the scale-length approach to solve 2D Poissons equation.

Design strategy of localized halo profile for achieving sub-50 nm bulk MOSFET

Abstract This paper presents a design strategy to optimize short-channel effects with localized halo profile for achieving sub-50 nm bulk MOSFET devices. With the optimal choice of the location of heavily doped halo, it can be simultaneously accomplished to improve the roll-off of threshold voltage and to relieve drain leakage current without raising the low threshold voltage. To reduce the impact of heavy halo doping concentration on the threshold voltage, it is essential to have a deep and short enough halo doping profile. The halo-to-extension spacing is the most effective design parameter to control the band-to-band leakage current and the threshold-voltage roll-off. With adequate halo-to-extension spacing, a much heavier halo doping concentration can be used to suppress the roll-off of threshold voltage without raising the drain leakage current. The sidewall oxide of the insulated shallow extension structure demonstrates the feasibility of the precise control of the halo-to-extension spacing to achieve a sub-50 nm bulk MOSFET with fully CMOS compatible process.

Effect of Rapid Thermal Annealing in N2 and Stacked Layer on SiO2?Al2O3?SiO2 Characteristics for Interpoly Silicon Dielectrics

In this paper, we present a thorough investigation of the physical and electrical characteristics of a SiO2/Al2O3/SiO2 (OAO) stack film. The crystallization temperature of an aluminum oxide (Al2O3) material of 9.2 nm thickness is about 925 °C, and leakage current is determined by trap-assisted tunneling (TAT) in the low E-field region owing to grain boundary formation. Nevertheless, crystalline Al2O3 can increase dielectric constant, lower band gap, and cause offset of conduction band (ΔEC); thus, a lower leakage is obtained in high E-field region. Comparing various films with the scheme of SiO2/Al2O3/SiO2 and presented at various post deposition annealing (PDA) temperatures, it is found that the top oxide thickness and crystallization temperature of the Al2O3 material play key factors for high electric strength and electron trapping. Our experiment demonstrated that a specific SiO2/Al2O3/SiO2 stack film incorporated with an appropriate thermal budget for Al2O3 annealing can be utilized for future NAND flash memory cells.

A Comprehensive Parameterized Model of Phase-Change Memory Cell for HSPICE Circuit Simulation

A comprehensive phase-change memory (PCM) HSPICE model with a simplified and flexible parameterized function was proposed and developed in this work. To extract the specific device parameters relevant to the cell characteristics for the establishment of PCM HSPICE model, a novel PCM cell with double-confinement structure was fabricated and electrically characterized. Several interrelated functional circuits were used to totally describe the characteristics of PCM cell and incorporated into a two-terminal HSPICE model. Based on this flexible model with designated device parameters, the programming characteristics of the double-confined cell including the determined static and dynamic programming states and the pulse-dependent and current-induced phase-transition behaviors can be accurately emulated. The simulation results show a good agreement with the experimental current–voltage (I–V) and resistance–current (R–I) curves, implying the feasibility and accuracy of the PCM HSPICE model. Therefore, the PCM HSPICE model developed in this work is applicable to future PCM chip designs.

Dependences of short-channel effect on doping profiles for nanoscale metal-oxide-semiconductor field-effect transistor

The analytical dependences of the short-channel effect on the channel and source/drain doping profiles are presented for currently nanoscale metal–oxide–semiconductor field-effect transistor (MOSFET). The scale-length approach is used for determining the channel potential from two-dimensional Poissons equation and the effective-doping model is applied for attaining short-channel effect from the potential solutions. The exponential dependences of threshold voltage roll-off on channel length can be retained for all kinds of doping profiles. However, the retrograde channel improves the short-channel effect by reducing its scale-length. The ultra-shallow junction relieves the threshold voltage roll-off by having a smaller coefficient for the exponential term. The effects of laterally nonuniform profiles for short-channel effect can be clarified by their effective scale-lengths. The halo doped channel provides a smaller effective scale-length to counteract short-channel effect, while the graded junction plays an opposite role to the halo doping with an enlarged effective scale-length. Without any fitting factors, excellent agreements between the numerical results and these models are obtained for wide ranges of device technologies into nanoscale regime.

A Simple and Useful Layout Scheme to Improve the CDM Robustness for the Input Buffer

It has been reported that the charged-device model (CDM) robustness of an IC strongly depends on the layout and function of the circuit and the package type [1]. However, the package type and circuit function are often not the items that could be changed. So, the only way the design house can do for CDM improvemen t is to revise the circuit layout. Except the interface circuit [2 ], however, what kind of circuit layout is susceptible to the CDM st ress is still unknown until now.

Effect of Mixed-Mode Electrical Stress on High-Frequency and RF Power Characteristics of SiGe Hetero-Junction Bipolar Transistors

In this study, we investigate the hot-carrier stress effects on the high-frequency and RF power characteristics of Si/SiGe hetero-junction bipolar transistors (HBTs). By simultaneously applying a high collector current density and a high collector–base voltage on Si/SiGe HBTs, because hot carriers will be induced; they will then degrade device performance. This is interesting because this stress condition is similar to the DC bias condition of a current source RF power amplifier, termed as the mixed-mode stress. We find that not only the high-frequency characteristic is adversely affected by but also the output power performance of Si/SiGe HBTs suffers from this electrical stress. In addition, we found that the degradations of the high-frequency and power characteristics of such HBTs are worse in constant-base-current measurement than in constant-collector-current measurement. We finally examined the degradations in terms of parasitic resistance and the ideality factors of base and collector currents using a large-signal model.

Investigation of Sidewall Oxidation on WSix Gates for Nano-Scale NAND Flash Memory Cells

Extrusions on W–polycide (WSix) gate sidewalls, sheet resistance (Rs), and device characteristics as well as memory cell performance for 70 nm NAND flash memory cells are investigated. To prevent the formation of unstable W–Si–O compounds, oxidation of WSix gate sidewalls prior to oxygen plasma ashing for source/drain photo resist removal is implemented, and then WSix extrusion can be absolutely suppressed. Moreover, the sheet resistance of a WSix gate can be improved near 40% by additional sidewall oxidation due to enlarged grain size and reduction in surface roughness; thus, the program voltage of memory cells can be significantly improved more than 1 V. Simultaneously, the saturation current of n-type metal–oxide–semicondutor field effect transistor (NMOSFET) shifts less than 4%, and cell threshold voltage fluctuations resulting from floating gate coupling are not obviously changed.