Chun Wong

Energy-aware runtime scheduling for embedded-multiprocessor SOCs

This task-scheduling method for embedded systems combines the low runtime complexity of a design-time scheduling phase with the flexibility of a runtime scheduling phase.

Managing dynamic concurrent tasks in embedded real-time multimedia systems

This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way. A two-phase scheduling method is used for that purpose. By exploring the Pareto curves and scenarios generated at design time, the run-time scheduler can easily find a good scheduling at a very low overhead, satisfying the system constraints and minimizing the energy consumption. A real-life example from a 3D quality of service kernel is used to show the effectiveness of our method.

Task concurrency management methodology to schedule the MPEG4 IM1 player on a highly parallel processor platform

This paper addresses the concurrent task management of complex multi-media systems, like the MPEG4 IM1 player, with emphasis on how to derive energy-cost vs time-budget curves through task scheduling on a multi-processor platform. Starting from the original “standard” specification, we extract the concurrency originally hidden by implementation decisions in a “grey-box” model. Then we have applied two high-level transformations on this model to improve the task-level concurrency. Finally, by scheduling the transformed task-graph, we have derived energy-cost vs time-budget curves. These curves will be used to get globally optimized design decisions when combining subsystems into one complete system or to be used by a dynamic scheduler. The results on the MPEG4 IM1 player confirm the validity of our assumptions and the usefulness of our approach.

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platformsgives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are concurrent in the sense that multiple subsystems can be running simultaneously. Also, these applications are so dynamic at run-time that the designs based on the worst case execution times are inefficient in terms of resource allocation (e.g., energy budgets). A novel systematical approach is clearly necessary in the area of system-level design for the embedded systems where those concurrent and dynamic applications are mapped. This material is mainly based on research at IMEC and its international university network partners in this area in the period 1997-2006. In order to deal with the concurrent and dynamic behaviors in an energy-performance optimal way, we have adopted a hierarchical system model (i.e., the gray-box model) that can both exhibit the sufficient detail of the applications for design-time analysis and hide unnecessary detail for a low-overhead run-time management. We have also developed a well-balanced design-time/run-time combined task scheduling methodology to explore the trade-off space at design-time and efficiently handle the system adaptations at run-time. Moreover, we have identified the connection between task-level memory/communication management and task scheduling and illustrated how to perform the task-level memory/communication management in order to obtain the design constraints that enable the this connection. A fast approach is also shown to estimate at the system-level, the energy and performance characterization of applications executing on the target platform processors.

Task concurrency analysis and exploration of visual texture decoder on a heterogeneous platform

The emergence of mobile multimedia terminals has given rise to growing demands for power-efficient and scalable image transmission. Visual texture coding (VTC) has attracted increasing attention due to its scalability when transmitting still images. Nowadays, the implementation of such VTC decoders has not yet considered the need of energy performance trade-offs at the system-level. We have applied systematic system-level design techniques to analyze the VTC decoder and explore its timing-energy trade-off space by using our concurrent task scheduling exploration techniques. The presented approach allows a system designer to select the optimal heterogeneous platform configuration for a given speed of the VTC decoder while minimizing the global energy consumption.

Dynamic Memory Oriented Transformations in the MPEG4 IM1-Player on a Low Power Platform

In this paper we propose several system-level transformations that allow to reduce the dynamic memory requirements of complex real-time multi-media systems. We demonstrate these transformations on the protocol layer of the MPEG4 IM1-player. As a consequence, up to 20% of the global power consumption of the protocol subsystem can be eliminated, which is significant due to the programmable processor target. The entire MPEG4 description is assumed to be mapped on a heterogeneous platform combining several software processors and hard-ware accelerators.

Mapping the MPEG-4 visual texture decoder: a system-level design technique based on heterogeneous platforms

This article presents automated techniques supporting the design-time scheduling phase of a unique approach for managing concurrent tasks of dynamic real-time applications mapped on a heterogeneous platform with different types of software and hardware components. This approach is based on design-time exploration, which results in a set of schedules and assignments for each task, represented by Pareto curves. At run-time, a low complexity scheduler selects an optimal combination of working points, exploiting the dynamic and nondeterministic behavior of the system. The combined approach leads to significant overall power savings compared to state-of-the-art dynamic voltage scaling techniques. The design-time generated Pareto curves can also be used by the application designer to effectively make quantitative tradeoffs between system cost and performance.

Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems

Publisher Summary This chapter presents a novel approach toward the management of concurrent tasks in dynamic real-time applications. The quality of the mapping can greatly affect both performance and energy consumption. It discusses a methodology to map the applications in a cost-efficient way onto a heterogeneous embedded multiprocessor platform. This approach is based on a design–time exploration, which results in a set of schedules and assignments for each task, represented by Pareto curves. At run time, a low-complexity scheduler selects an optimal combination of working points, exploiting the dynamic and nondeterministic behavior of the system. This approach leads to significant power saving compared with state-of-the art dynamic voltage scaling (DVS) techniques because of three major contributions. First, the effective combination of an intratask detailed design-time exploration and a low-overhead runtime scheduler. Second, the design–time scheduler provides a whole range of energy–time tradeoff points (Pareto curves) instead of a single fixed solution to use at run time. Third, by considering the information provided on run-time applications, and introducing a scenario approach to avoid the use of worst-case execution time (WCET) estimation, hard real-time constraints can still be met. In future, this work can be extended to provide automatic tool support for code synthesis and real-time operating system (RTOS) integration. A research is also underway on concurrency improving transformations to produce a better gray-box model as a starting point for the scheduler stage.