Johan Vounckx

Managing dynamic concurrent tasks in embedded real-time multimedia systems

This paper addresses the problem of mapping an application, which is highly dynamic in the future, onto a heterogeneous multiprocessor platform in an energy efficient way. A two-phase scheduling method is used for that purpose. By exploring the Pareto curves and scenarios generated at design time, the run-time scheduler can easily find a good scheduling at a very low overhead, satisfying the system constraints and minimizing the energy consumption. A real-life example from a 3D quality of service kernel is used to show the effectiveness of our method.

Reconfiguration and Checkpointing in Massively Parallel Systems

Despite the improvements in hardware design massively parallel systems lack on dependability due to the huge amount of components these systems consist of. One possibility to introduce fault-tolerance into such systems is backward error recovery where failed modules can be replaced by spares. The ESPRIT Project 6731 “A Practical Approach to Fault-Tolerant Massively Parallel Systems” follows such an approach and covers the aspects of error detection, diagnosis, checkpointing and reconfiguration. Target systems are multi-computers consisting of grid-wise connected modules using message passing. A first implementation will be made for the Parsytec GCel under PARIX. This paper focuses on recovery by reconfiguration and checkpointing. The project is based on switching in spares and routing around failed components via virtual links (interval routing). For the recovery a user-driven as well as a user-transparent approach are provided based on the new recovery-line-manager.

Task concurrency analysis and exploration of visual texture decoder on a heterogeneous platform

The emergence of mobile multimedia terminals has given rise to growing demands for power-efficient and scalable image transmission. Visual texture coding (VTC) has attracted increasing attention due to its scalability when transmitting still images. Nowadays, the implementation of such VTC decoders has not yet considered the need of energy performance trade-offs at the system-level. We have applied systematic system-level design techniques to analyze the VTC decoder and explore its timing-energy trade-off space by using our concurrent task scheduling exploration techniques. The presented approach allows a system designer to select the optimal heterogeneous platform configuration for a given speed of the VTC decoder while minimizing the global energy consumption.

The FTMPS-Project: Design and Implementation of Fault-Tolerance Techniques for Massively Parallel Systems

The FTMPS-project provides a solution to the need for faulttolerance in large systems. A complete fault-tolerance approach is developed and being implemented. The built-in hardware error-detection features combined with software error-detection techniques provide a high coverage of transient as well as permanent failures. Combined with the diagnosis software, the necessary information for the OSS (statistics and visualisation) and the possibly reconfiguration is collected. Backward error recovery based on checkpointing and rollback, is implemented.

Hierarchical task scheduler for interleaving subtasks on heterogeneous multiprocessor platforms

Nowadays, the system-on-a-chip (SoC) has integrated more processors onto a single chip. Applications are also consisting of multiple (sub) tasks that are presented as different source code which can be partly executed concurrently. However, the subtask-level parallelism inside a single task is often too limited to fully utilize all the parallel processors and results in many slacks on processors. To better use the processors, subtasks of multiple tasks will have to be executed in an interleaving fashion. This paper proposes design-time algorithms to interleave subtasks based on the separated schedules of tasks. This interleaver can be considered as part of a hierarchical scheduler to steer the code generation of very complex applications with many tasks. The scheduling experiments show that the execution time can be shortened by 20%-30% when interleaving two tasks against the sequential execution without subtask interleaving. Moreover, the differences between the solutions given by our scheduling algorithm and the optimal solutions are less than 6% for up to 20 subtasks.

Mapping the MPEG-4 visual texture decoder: a system-level design technique based on heterogeneous platforms

This article presents automated techniques supporting the design-time scheduling phase of a unique approach for managing concurrent tasks of dynamic real-time applications mapped on a heterogeneous platform with different types of software and hardware components. This approach is based on design-time exploration, which results in a set of schedules and assignments for each task, represented by Pareto curves. At run-time, a low complexity scheduler selects an optimal combination of working points, exploiting the dynamic and nondeterministic behavior of the system. The combined approach leads to significant overall power savings compared to state-of-the-art dynamic voltage scaling techniques. The design-time generated Pareto curves can also be used by the application designer to effectively make quantitative tradeoffs between system cost and performance.

Cost-Efficient Mapping of Dynamic Concurrent Tasks in Embedded Real-Time Multimedia Systems

Publisher Summary This chapter presents a novel approach toward the management of concurrent tasks in dynamic real-time applications. The quality of the mapping can greatly affect both performance and energy consumption. It discusses a methodology to map the applications in a cost-efficient way onto a heterogeneous embedded multiprocessor platform. This approach is based on a design–time exploration, which results in a set of schedules and assignments for each task, represented by Pareto curves. At run time, a low-complexity scheduler selects an optimal combination of working points, exploiting the dynamic and nondeterministic behavior of the system. This approach leads to significant power saving compared with state-of-the art dynamic voltage scaling (DVS) techniques because of three major contributions. First, the effective combination of an intratask detailed design-time exploration and a low-overhead runtime scheduler. Second, the design–time scheduler provides a whole range of energy–time tradeoff points (Pareto curves) instead of a single fixed solution to use at run time. Third, by considering the information provided on run-time applications, and introducing a scenario approach to avoid the use of worst-case execution time (WCET) estimation, hard real-time constraints can still be met. In future, this work can be extended to provide automatic tool support for code synthesis and real-time operating system (RTOS) integration. A research is also underway on concurrency improving transformations to produce a better gray-box model as a starting point for the scheduler stage.

Reconfiguration of massively parallel systems

The reconfiguration approach presented in this paper provides a solution to the need for fault tolerance in large systems. The developed techniques all have a data complexity and an execution time complexity less than proportional to the number of nodes in the system. Hence the approach is extremely suited for massively parallel systems. The reconfiguration strategy consists of four different subtasks, repartitioning (each application must have sufficient working processors), loading of injured networks, remapping (to replace faulty processors by working ones) and deadlock-free fault tolerant compact routing.