Pol Marchal

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

In this paper key design issues and considerations of a low-cost 3-D Cu-TSV technology are investigated. The impact of TSV on BEOL interconnect reliability is limited, no failures have been observed. The impact of TSV stress on MOS devices causes shifts, further analysis is required to understand their importance. Thermal hot spots in 3-D chip stacks cause temperature increases three times higher than in 2-D chips, necessitating a careful thermal floorplanning to avoid thermal failures. We have monitored for ESD during 3-D processing and have found no events take place, however careful further monitoring is required. The noise coupling between two tiers in a 3-D chip-stack is 20 dB lower than in a 2-D SoC, opening opportunities for increased mixed signal system performance. The impact on digital circuit performance of TSVs is accurately modeled with the presented RC model and digital gates can directly drive signals through TSVs at high speed and low power. Experimental results of a 3-D Network-on-Chip implementation demonstrate that the NoC concept can be extended from 2-D SoC to 3-D SoCs at low area (0.018 ) and power (3%) overhead.

Comprehensive analysis of the impact of single and arrays of through silicon vias induced stress on high-k / metal gate CMOS performance

As scaling becomes increasingly difficult, 3D integration has emerged as a viable alternative to achieve the requisite bandwidth and power efficiency challenges. However mechanical stress induced by the through silicon vias (TSV) is one of the key constraints in the 3D flow that must be controlled in order to preserve the integrity of front end devices. For the first time an extended and comprehensive study is given for the stress induced by single- and arrayed TSVs and its impact on both analog and digital FEOL devices and circuits. This work provides a complete experimental assessment and quantifies the stress distribution and its effect on front end devices. By using a combined experimental and theoretical approach we provide a framework that will enable stress aware design and the right definition of keep out zone and ultimately save valuable silicon area.

Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

To ensure low power consumption while maintaining flexibility and performance, future Systems-on-Chip (SoC) will combine several types of processor cores and data memory units of widely different sizes. To interconnect the IPs of these heterogeneous platforms, Networks-on-Chip (NoC) have been proposed as an efficient and scalable alternative to shared buses. NoCs can provide throughput and latency guarantees by establishing virtual circuits between source and destination. State-of-the-art NoCs currently exploit Time-Division Multiplexing (TDM) to share network resources among virtual circuits, but this typically results in high network area and energy overhead with long circuit set-up time.We propose an alternative solution based on Spatial Division Multiplexing (SDM). This paper describes our first design of an SDM-based network, discusses design alternatives for network implementation and shows why SDM should be better adapted to NoCs than TDM for a limited number of circuits.Our case study clearly illustrates the advantages of our technique over TDM in terms of energy consumption, area overhead, and flexibility. SDM thus deserves to be explored in more depth, and in particular in combination with TDM in a hybrid scheme.

Stackable memory of 3D chip integration for mobile applications

Stacking memory with 3D chip integration technology could provide the much needed bandwidth and memory density for mobile applications at low power. The contribution of this paper is to review the desired attributes of a stackable memory from system aspects and discuss its implementation challenges.

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogenous Platforms

Systematic Methodology for Real-Time Cost-Effective Mapping of Dynamic Concurrent Task-Based Systems on Heterogeneous Platformsgives an overview of the state-of-the-art in system-level design trade-off explorations for concurrent tasks running on embedded heterogeneous multiple processors. The targeted application domain covers complex embedded real-time multi-media and communication applications. Many of these applications are concurrent in the sense that multiple subsystems can be running simultaneously. Also, these applications are so dynamic at run-time that the designs based on the worst case execution times are inefficient in terms of resource allocation (e.g., energy budgets). A novel systematical approach is clearly necessary in the area of system-level design for the embedded systems where those concurrent and dynamic applications are mapped. This material is mainly based on research at IMEC and its international university network partners in this area in the period 1997-2006. In order to deal with the concurrent and dynamic behaviors in an energy-performance optimal way, we have adopted a hierarchical system model (i.e., the gray-box model) that can both exhibit the sufficient detail of the applications for design-time analysis and hide unnecessary detail for a low-overhead run-time management. We have also developed a well-balanced design-time/run-time combined task scheduling methodology to explore the trade-off space at design-time and efficiently handle the system adaptations at run-time. Moreover, we have identified the connection between task-level memory/communication management and task scheduling and illustrated how to perform the task-level memory/communication management in order to obtain the design constraints that enable the this connection. A fast approach is also shown to estimate at the system-level, the energy and performance characterization of applications executing on the target platform processors.

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support

In todays multiprocessor SoCs (MPSoCs), parallel programming models are needed to fully exploit hardware capabilities and to achieve the 100 Gops/W energy efficiency target required for ambient intelligence applications. However, mapping abstract programming models onto tightly power-constrained hardware architectures imposes overheads which might seriously compromise performance and energy efficiency. The objective of this work is to perform a comparative analysis of message passing versus shared memory as programming models for single-chip multiprocessor platforms. Our analysis is carried out from a hardware-software viewpoint: we carefully tune hardware architectures and software libraries for each programming model. We analyze representative application kernels from the multimedia domain, and identify application-level parameters that heavily influence performance and energy efficiency. Then, we formulate guidelines for the selection of the most appropriate programming model and its architectural support

Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy

Energy scalable architectures and circuits for SDRs are proposed, for both a reconfigurable RF front-end and a heterogeneous multiprocessor SoC in a baseband platform. A performance/energy manager dynamically exploits the energy scalability and the dynamics in application requirements and propagation environment, realizing low-power operation. For the transmitter, the energy-scalability is translated to an average system-level energy-efficiency improvement of up to 40%.

Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips

3D stacking of dies is a promising technique to allow miniaturization and performance enhancement of electronic systems. The complexity of the interconnection structures, combined with the reduced thermal spreading in the thinned dies and the poorly thermally conductive adhesives complicate the thermal behavior of a stacked die structure. The same dissipation will lead to higher temperatures and a more pronounced temperature peak in a stacked die package compared to a single die package. Therefore, the thermal behavior in a 3D-IC needs to be studied thoroughly. In this paper, a steady state and transient analysis is presented for hot spots in 3D stacked structures. For this analysis, dedicated test chips with integrated heaters and temperature sensors are used to assess the temperature profile in the different tiers of the stack and to investigate the impact of TSVs on the temperature profile. This experimental set-up is used to evaluated and improve the thermal models for the 3D stacks.

Physical design implementation of segmented buses to reduce communication energy

The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, segmented buses have gained interest in the architectural community. However, the netlist topology and the physical design stage significantly influence the final communication energy cost. We present in this paper an automated way to implement a netlist consisting of hard macro blocks, which are interconnected with heavily segmented buses in an energy optimal fashion for communication. We optimize the network wires energy dissipation in two separate, but related steps: minimizing the number of segments for active communication paths at the first step (block ordering), followed by the activity aware floorplanning step to minimize the physical length of these segments. Energy gains of up to a factor of 4 are achieved compared to a standard system implementation using a shared bus. Especially, the block ordering step contributes significantly to the network energy optimization process.

SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms

Heterogeneous multi-processors platforms are an interesting option to satisfy the computational performance of dynamic multi-media applications at a reasonable energy cost. Today, almost no support exists to energy-efficiently manage the data of a multi-threaded application on these platforms. In this paper we show that the assignment of data of dynamically created/deleted tasks to the shared memory has a large impact on the energy consumption. We present two dynamic memory allocators which solve the bank assignment problem for shared multi-banked SDRAM memories. Both allocators assign the tasksý data to the available SDRAM banks such that the number of page-misses is reduced. We have measured large energy savings with these allocators compared to existing dynamic memory allocators for several task-sets based on MediaBench[5].