Chih-Feng Wu

Joint Carrier Synchronization and Equalization Algorithm for Packet-Based OFDM Systems Over the Multipath Fading Channel

In this paper, a joint carrier synchronization and equalization algorithm is presented for orthogonal frequency-division multiplexing (OFDM) systems in the tracking stage. Based on the minimum mean-square-error (MMSE) criterion, the cost function of the joint algorithm is proposed to minimize the mean square error (MSE), namely, the uncoded bit error rate (BER), on each subchannel and to further lower the carrier frequency jitter concurrently. The carrier synchronization scheme with multirate processing is a dual-loop structure, which is composed of outer and inner loops. The outer loop is a frequency-tracking loop that deals with the phase offset, which is induced by the carrier frequency offset (CFO), in the time domain. The inner loop is a phase-tracking loop to cope with the phase distortions, which are caused by the carrier frequency error and the channel phase variation, on each subcarrier in the frequency domain. There is a gain equalization loop to compensate the magnitude distortion on each subchannel. Furthermore, the closed-loop stability of the carrier synchronization loop is particularly explored for the loop delay induced by hardware realization. Many simulations are done for the additive white Gaussian noise (AWGN) and the multipath frequency-selective fading channels to show that the joint algorithm not only accurately estimates and compensates the CFO and the channel impairment but also provides the cost-effective feature compared with the considered algorithms.

A 256-point dataflow scheduling 2×2 MIMO FFT/IFFT processor for IEEE 802.16 WMAN

In this paper, an efficient solution of MIMO FFT/IFFT processor for IEEE 802.16 WMAN is presented. By applying the proposed mixed-radix dataflow scheduling (MRDS) technique, the effective hardware utilization can be raised to 100%. Therefore, a single butterfly unit within each pipeline stage is sufficient to deal with the two data sequences, and the hardware complexity is significantly reduced. The proposed FFT/IFFT processor has been emulated on the FPGA board. The signal-to-quantization noise ratio (SQNR) is over 44 dB for QPSK and 16/64-QAM signals. Furthermore, a test chip has been designed using standard 0.18-mum CMOS technology with a core area of 887 times 842 mum2. According to the post-layout simulation results, the design consumes 46 mW at 64 MHz operating frequency, which meets the maximum throughput requirements of IEEE 802.16 WMAN.

Joint Carrier Synchronization and Equalization for OFDM Systems Over Multipath Fading Channel

In this paper, a joint carrier synchronization and equalization algorithm is proposed for OFDM systems in the tracking stage. Significantly, the carrier synchronization scheme is a dual-loop, which is composed of an outer and an inner loops, with the multirate processing to eliminate the carrier frequency offset and the channel phase variation. In addition, the gain equalization loop is employed to compensate the magnitude distortion on each subchannel in the frequency domain. Based on MMSE criterion, the cost function of the joint algorithm is presented to minimize the decision error on each subchannel and, further, lower the uncoded BER concurrently. Besides, the subchannel SDR is derived in terms of the powers of the phase and gain jitters. Considering a figure of merit for CFO RMS error, the improvement for the joint algorithm is about 1-order at least compared with the considered algorithms. According to BER derivation and simulation in an AWGN channel, SNR losses at BER=10-6 from the theory to the derivation and simulation of the proposed algorithm are about 0.1 dB (derivation) and 0.4 dB (simulation). The proposed joint algorithm can estimate and compensate the carrier frequency offset as well as channel distortion accurately.

I/Q imbalance compensation and channel equalization algorithm for MISO-OFDM systems

In this paper, both the I/Q imbalance compensation and the channel equalization algorithm are proposed for space-time-block-code (STBC) MISO-OFDM systems. The I/Q imbalance compensation scheme is composed of self-calibration and tracking processes. The self-calibration process is further divided into two stages, symmetric- and anti-symmetric-tone, employed to extract the gain and the phase mismatches of transmitter (Tx) and receiver (Rx) I/Q imbalance for end-user in system power-on. According to the results of self-calibration process, both pre-and post-compensation block is presented to eliminate the Tx and Rx I/Q imbalances of end-user, respectively. In addition, the remote Tx I/Q imbalance compensation can be merged into the channel equalization process, based on MMSE criterion, on each subchannel.

Cost-efficient design and fixed-point analysis of IFFT/FFT processor chip for OFDM systems

In this paper, a cost-efficient raultiplierless IFFT/FFT processor with its fixed-point error analysis is presented. The IFFT/FFT processor employs the radix-2/4/8 algorithm, and a proposed classification of twiddle factors (TW) and hardware sharing are used to minimize the nonzero bits of the shift-and-adds operations. After the appropriate wordlengths (WL) of the TWs and the IFFT/FFT processor input are chosen by the proposed fixed-point quantization noise analysis, a hardwarelike fixed-point simulation model of the IFFT/FFT processor is used to develop the Verilog RTL code. The proposed IFFT/FFT processor can achieve packet error rate(PER) less than 0.1 for the test vehicle IEEE 802.11a single-input-single-output (SISO)-OFDM system and slight symbol error rate(SER) loss for the IEEE 802.11n multi-input-multi-output (MIMO)-OFDM system. The core area of the one processor chip is 0.57umx0.565um with 0.18um CMOS process. Besides, the power consumption is 7.74 mW with 1.8 V supply voltage and 40 Mhz system clock.

Design and analysis of cost-efficient IFFT/FFT processor chip for wireless OFDM systems

In this paper, a cost-efficient IFFT/FFT processor with its fixed-point analysis is presented for wireless orthogonal frequency division multiplexing (OFDM) system. The IFFT/FFT processor is multiplierless architecture, and the nonzero bits of twiddle factors (TW) are minimized to reduce the structure (or the number of the hardwired adder) by the proposed classification of TWs and hardware sharing. On the other hand, the minimum wordlength (WL) of the TWs and input signals can be determined by the fix-point analysis. The proposed IFFT/FFT processor can achieve packet error rate(PER); 0.1 for the test vehicle IEEE 802.11a single-input-single-output(SISO)-OFDM system and slight symbol error rate(SER) loss for the IEEE 802.11n multi-input-multi-output(MIMO)-OFDM system. The core area of the one processor chip is 0.57um×0.565um with 0.18um CMOS process. Besides, the power consumption is 7.74 mw with 1.8 V supply voltage and 40 Mhz system clock.

Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems - Loop-Delay Analysis and Complexity Consideration

In this paper, the loop-delay analysis and the com- plexity consideration of the joint carrier synchronization and equalization algorithm for OFDM systems are presented. As a result, the loop-delay induces an additional phase lag and further gives rise to instability for the dual-loop carrier synchronization loop. In addition, the complexity consideration shows that the presented algorithm definitely accomplishes the cost-effective feature compared with the previous works. I. INTRODUCTION OFDM system is very sensitive to the carrier frequency offset (CFO), which induces the intercarrier interference (ICI) and thus degrades the system performance. The joint carrier synchronization and equalization algorithm (1) is presented to combat the residual CFO and the channel equalization concurrently for OFDM systems in the tracking stage over the multipath fading channel. The cost function of the joint algorithm is derived to minimize the error power on each subchannel based on the minimum mean square error (MMSE) criterion. Therefore, the cost function J(·) on each subchannel can be expressed as

Joint Carrier Synchronization and Equalization Algorithm for OFDM Systems -- Closed-Loop Derivation

In this paper, the closed-loop derivation of the joint carrier synchronization and equalization algorithm for OFDM systems in the tracking stage are presented using the multirate DPLL and the fictitious sampler techniques. As a result, the carrier synchronization scheme is a dual-loop structure, outer and inner loops, which can be regarded as a proportional and a integral parts of DPLL respectively. Besides, the approximation and the stability of the dual-loop are also presented. On the other hand, the equalization scheme is a first-order closed-loop, based on LMS algorithm, for gain equalization on each subchannel.

A MIMO-OFDM digital baseband receiver design with adaptive equalization technique for IEEE 802.16 WMAN

In this paper, a 2×2 MIMO-OFDM digital baseband receiver for IEEE 802.16 WMAN-OFDM PHY is presented. The inner receiver design includes the timing and carrier frequency synchronization, the channel estimation and the MIMO detection with adaptive equalization technique. In order to enhance the robustness of the system, the BLMS algorithm is derived to track the channel variation for the Alamouti-scheme STBC FEQ. The simulation results demonstrate that the MIMO receiver with adaptive equalization technique has superior SER performance over frequency selective fading channel.

Cost efficient FEQ implementation for IEEE 802.16a OFDM transceiver

Based on SR transformation, a cost efficient FEQ is proposed for OFDM transceiver of IEEE 802.16a WMAN without SNR loss over the multipath fading channel. The cost efficient FEQ is composed of three parts: channel estimation, filtering and updating processes. Significantly, the computing complexity of multiplication for the cost efficient approach can totally yield 19% reduction compared with the conventional approach. In view of the memory arrangement in VLSI design, the area and power can be decreased by 70% and 50% respectively for the channel estimation. In the updating, 18% reduction is obtained for both area and power. According to the uncoded SER simulation, the proposed approach is identical with the conventional approach. Finally, the cost efficient FEQ is demonstrated by FPGA board.