Chung-chi Lin

The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing

This paper presents an efficient VLSI design of bicubic convolution interpolation for digital image processing. The architecture of reducing the computational complexity of generating coefficients as well as decreasing number of memory access times is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Based on our technique, the high-speed VLSI architecture has been successfully designed and implemented with TSMC 0.13 mum standard cell library. The simulation results demonstrate that the high performance architecture of bi-cubic convolution interpolation at 279 MHz with 30643 gates in a 498times498 mum chip is able to process digital image scaling for HDTV in real-time.

Real-time FPGA architecture of extended linear convolution for digital image scaling

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The presented architecture is implemented on the Virtex-II FPGA has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 104 MHz with 379 LBs is able to process digital image scaling.

The VLSI Design of Winscale for Digital Image Scaling

The resolution of digital displays has been improved with increment of the display sizes of those devices. The digital image scaling algorithm, winscale, is suitable for digital display devices in various resolutions; nevertheless, the computational complexity of winscale algorithm is not able to process in real-time. In this paper, we implement an efficient VLSI architecture design of winscale algorithm. The core consists of coordinate accumulator, pixel orientation unit, area calculation unit, and multiplication-addition unit. Base on our technique, the high speed VLSI architecture has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of image scaling at 130.24 MHz with 17414 gates in a 450 x 450 mum core area of chip is able to process digital image scaling for HDTV in real-time.

An Efficient Architecture of Extended Linear Interpolation for Image Processing

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 25980 gates in a 450 × 450μm^2 chip is able to process digital image scaling for HDTV in real-time.

Motion Adaptive De-interlacing with Local Scene Changes Detection

This paper presents a motion adaptive de- interlacing technique with precise interfield information by local scene changes detection. Scene changes happen fairly often in film broadcasting and they tend to destabilize the quality of performance while de-interlacing technique is utilized. Our local scene change detection method for de-interlacing uses the precise interfield information as interpolation. The simulation results indicate that increasing the precision and stability of the interfield information promotes quality of video sequence.

A Low-cost VLSI Design of Extended Linear Interpolation for Real Time Digital Image Processing

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Based on the approach, the low-cost hardware architecture with digital image scaling is designed under the real-time requirement. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. The presented architecture is implemented on the Virtex-II FPGA, and the VLSI architecture has been successfully designed and implemented with TSMC 0.13 mum standard cell library. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 267 MHz with 26200 gates in a 452times452 mum2 chip is able to process digital image scaling for HDTV in real-time.

An Efficient Video De-interlacing with Scene Change Detection

An efficient video de-interlacing technique with scene change detection is proposed and its performances are examined. Scene changes happen quite often in film broadcasting and they tend to destabilize the quality of performance such as jagged effect, blurred effect, and artifacts effect, while de-interlacing technique is utilized. Therefore, the issue of scene change needs to be addressed with de-interlacing process. In the proposed method, de-interlacing begins with scene change detection, which is to ensure that the interfield information is used correctly. To improve the quality of de-interlacing, the factors of scene change are taken into account when de-interlacing techniques are applied. The simulation results show that the proposed algorithm exhibits better performances than other interpolation algorithms

A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information

Scene changes occur frequently in film broadcasting, and tend to destabilize the performance with blurred, jagged, and artifacts effects when de-interlacing methods are utilized. This paper presents an efficient VLSI architecture of video de-interlacing with considering scene change to improve the quality of video results. This de-interlacing architecture contains three main parts. The first is scene change detection, which is designed based on examining the absolute pixel difference value of two adjacent even or odd fields. The second is background index mechanism for classifying motion and non-motion pixels of input field. The third component, spatial-temporal edge-based median filter, is used to deal with the interpolation for those motion pixels. Comparing with the existed de-interlacing approaches, our architecture design can significantly ameliorate the PSNRs of the video sequences with various scene changes; for other situations, it also maintains better performances. The proposed architecture has been implemented as a VLSI chip based on UMC 0.18-μm CMOS technology process. The total gate count is 30114 and its layout area is about 710 × 710-μm. The power consumption is 39.78 mW at working frequency 128.2 MHz, which is able to process de-interlacing for HDTV in real-time.

An efficient convolution interpolation kernel for digital image scaling

This paper presents an efficient extended linear convolution interpolation method for efficient scaling. The kernel of the extended linear convolution interpolation is built up of first-order polynomial and approximates the ideal sinc-function in interval [-2, 2]. The approach reduces the computational complexity of interpolation and the interpolation quality is compatible to that of bi-cubic convolution interpolations.

The VLSI design of de-interlacing with scene change detection

This paper presents an efficient video de-interlacing technique with scene change detection and its VLSI architecture design. Scene changes happen quite often in film broadcasting and they tend to destabilize the quality of performance such as jagged effect, blurred effect, and artifacts effect, while de-interlacing technique is utilized. Therefore, the issue of scene change needs to be addressed with de-interlacing process. In the proposed method, de-interlacing begins with scene change detection, which is to ensure that the interfield information is used correctly. To improve the quality of de-interlacing, the factors of scene change are taken into account when de-interlacing techniques are applied. Besides, based on our method, the high speed VLSI architecture has been designed and implemented. And the frequency of the chip is 110MHz that it could be real-time processing for HDTV