Wen-Kai Tsai

Real-time FPGA architecture of extended linear convolution for digital image scaling

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Our proposed method provides a simple hardware architecture design, low computation cost and is easy to implement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The presented architecture is implemented on the Virtex-II FPGA has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of extended linear interpolation at 104 MHz with 379 LBs is able to process digital image scaling.

The VLSI Design of Winscale for Digital Image Scaling

The resolution of digital displays has been improved with increment of the display sizes of those devices. The digital image scaling algorithm, winscale, is suitable for digital display devices in various resolutions; nevertheless, the computational complexity of winscale algorithm is not able to process in real-time. In this paper, we implement an efficient VLSI architecture design of winscale algorithm. The core consists of coordinate accumulator, pixel orientation unit, area calculation unit, and multiplication-addition unit. Base on our technique, the high speed VLSI architecture has been successfully designed and implemented. The simulation results demonstrate that the high performance architecture of image scaling at 130.24 MHz with 17414 gates in a 450 x 450 mum core area of chip is able to process digital image scaling for HDTV in real-time.

An Efficient Architecture of Extended Linear Interpolation for Image Processing

This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost and high-speed architecture with interpolation quality compatible to that of bi-cubic convolution interpolation. The method of reducing computational complexity of generating weighting coefficients is proposed. Based on the approach, the efficient hardware architecture is designed under real-time requirement. Compared to the latest bi-cubic hardware design work, the architecture saves about 60% of hardware cost. The architecture is implemented on the Virtex-II FPGA, and the high-speed VLSI has been successfully designed and implemented with TSMC 0.13μm standard cell library. The simulation results demonstrate that the efficient VLSI of extended linear interpolation at 267MHz with 25980 gates in a 450 × 450μm^2 chip is able to process digital image scaling for HDTV in real-time.

Block-Based Major Color Method for Foreground Object Detection on Embedded SoC Platforms

Background modeling and foreground object detection are crucial techniques for embedded image surveillance systems. The most popular and accurate methods are mostly pixel based, taking up more memory and requiring longer execution times. Thus, these techniques are not suitable for embedded platforms. This paper presents a block-based major color background modeling and a foreground detection algorithm that possesses efficient processing and low memory requirement in a complex scene, making them feasible for embedded platforms. Our proposed approach consumes 37% less memory and increases accuracy by at least 2% compared to existing methods. Last, implementing the object detection algorithm on the VIA VB8001 platform, we can achieve 22 frames per second for the benchmark video with image size 768 576.

High-accuracy background model for real-time video foreground object detection

Video foreground object detection faces the problems of moving backgrounds, illumination changes, chaotic motion in real word applications. This paper presents a hybrid pixel-based background (HPB) model, which is constructed by single stable record and multi-layer astable records after initial learning. This HPB model can be used for background subtraction to extract objects precisely in various complex scenes. Using the multi-layer astable records, we also propose a homogeneous background subtraction that can detect the foreground object with less memory load. Based on the benchmark videos, the experimental results show that single stable and 3-layer multi-layer astable records can be enough for background model construction and are updated quickly to overcome the background variation. The proposed approach can improve the average error rates of foreground object detection up to 86% when comparing with the latest works. Furthermore, our method can achieve real-time analysis for complex scenes on personal computers and embedded platforms.

Fast Fair Crossbar Scheduler for On-chip Router

This paper proposed a scheduling algorithm for a low-cost crossbar switch design in on-chip packet-switched micro-network. The scheduling algorithm is based on a distributed arbitration scheme over crossbar fabric. Each input port is designed with a mask circuit which can provide fair arbitration. As a result, our scheduler has lower power consumption because it does not need to toggle each node frequently. Experimental results show that designs utilizing our approach can reduce scheduling delay and hardware costs more than 43% and 49% respectively, as compared to those of the popular round robin algorithm. Based on the proposed scheme for 8-input scheduling circuit design, the critical delay is 0.98 ns and the power consumption is 98 muW with 50% traffic load at 100 MHz grant signal frequency in TSMC 0.18 mum technology

Image Object Detection and Tracking Implementation for Outdoor Scenes on an Embedded Soc Platform

This paper presents an Intelligent Surveillance System which can be used in real scenes. Our aim is to establish a reliable background from a complex one via a accurate segmentation method followed by object tracking. The system is able to continue tracking the objects regardless if the objects are overlapping or separate. The system uses the TI TMS320DM6446 Davinci development kit, inputs image sequence using a CCD Camera, executes the algorithms on the Davinci platform, and then display the execution results on a 352x240(NTSC CIF) or 720x480(NTSC D1) monitor. Based on the simulation results, the algorithm proposed by us achieves better results in varies ways, namely: functional practicality, detection effect, efficiency, the computational complexity, and so on.

A robust background modeling and foreground object detection using color component analysis

Background modeling and foreground object detection are crucial techniques for embedded image surveillance systems. The popular and accurate methods are mostly pixel based, taking up more memory and requiring longer execution times. Thus, these techniques are not suitable for embedded platforms. This paper presents a block-based major color background modeling and a foreground detection algorithm that possesses efficient processing and low memory requirement in a complex scene, making them feasible for embedded platforms. Our proposed approach consumes 37% less memory and increases accuracy by at least 2.5% compared to other existing methods. Last, implementing the object detection algorithm on the 2.83GHz CPU, we can achieve 26 frames per second for the benchmark video with image size 768×576.

Object detection using adaptive block-based background model

This paper propose an adaptable block-based background modeling and real time image object detection algorithm. In training step, we present adaptable block-based background model that uses major color number to determine the block size. This background model can reduce the memory consumption, efficiently. In detection step, we use one pixel to compare with background model. Then, it can reduce processing time. The experiment results show that we can save 33.9% memory space. Finally, we can achieve 27.25 frames per second for the benchmark video with image size 768×576.

Fast image moving object segmentation based on block texture for embedded system implementation

In this paper, we present a new moving object detection approach based on block texture. It can dramatically reduce the memory size when constructing the background model in a dynamic scene. The proposed background model and detection algorithm are suitable for implementing on embedded system platform which always has resource limitation. From the experimental results, our detection quality achieves 78% similarity in average. The memory consumption can be reduced 47.92% when comparing with the existing algorithms. Finally, the operation performance can be demonstrated on embedded system platform with 10 frames per second.