Tien-Yu Lo

A wide tuning range G m -C filter for multi-mode direct-conversion wireless receivers

A third-order channel selection filter for multi-mode direct-conversion receiver is presented. The filter is designed based on the Butterworth prototype with the target applications of bluetooth, cdma2000, wideband CDMA, and IEEE 802.11 a/b/g/n wireless LANs. Linear region MOS transistors are used to perform the voltage-to-current conversion. The wide tuning range can be achieved by the translinear loop followed by the linear voltage-to-current converter. Implemented in the TSMC 0.18-mum CMOS process, the measurement results show that the filter can operate with the cutoff frequency of 500 kHz to 20 MHz, and thus meet the requirement of different wireless applications. In the design, the maximum power consumption is 11.1 mW under a 1.2-V supply voltage. The figure of merit (FOM) is favorably compared with the other previously reported works.

A 1 GHz OTA-based low-pass filter with a high-speed automatic tuning scheme

A continuous-time 4th-order equiripple linear phase G m -C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined CMFF and CMFB circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining a negative resistor at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the Deep-NWELL technology. Through the use of the OTA as a building block with a modified automatic tuning scheme, the filter -3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The -43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two tone signals. Implemented in 0.18-mum CMOS process, the chip occupies 1mm2 and consumes 175 mW at a 1.5-V supply voltage.

A 1 GHz Equiripple Low-Pass Filter With a High-Speed Automatic Tuning Scheme

A continuous-time fourth-order equiripple linear phase Gm-C filter with an automatic tuning circuit is presented. A high speed OTA based on the inverter structure is realized. The combined common-mode feedforward and common-mode feedback circuit ensures the input and output common-mode stability. The gain performance could be maintained by combining an equivalent negative resistor circuit at the output nodes. Transconductance tuning can be achieved by adjusting the bulk voltage by using the deep-NWELL technology. The modified automatic tuning circuit relaxes the speed requirement of the tuning blocks. Through the use of the operational transconductance amplifier as a building block with the automatic tuning scheme, the filter - 3 dB cutoff frequency is 1 GHz with the group delay less than 4% variation up to 1.5 fc frequency. The - 43 dB of IM3 at filter cutoff frequency is obtained with -4 dbm two-tone signals. Implemented in 0.18-μ m CMOS process, the chip occupies 1 mm2 and consumes 175 mW at a 1.5-V supply voltage.

A high speed and high linearity OTA in 1-V power supply voltage

This paper proposes a high performance operational transconductance amplifier (OTA) which is based on the pseudo-differential architecture with addition of linearity improved circuits. The OTA is designed under low power supply voltage consideration while its gain, excess phase, and linearity are well maintained. A common-mode control system, including common-mode feedback (CMFB) and common-mode feedforward (CMFF) circuits, is added to ensure stability at high frequency. Results show that the topology can achieve the total harmonic distortion (THD) to the -56dB with 100MHz balanced differential input signals up to 300mVpp at 1-V supply voltage by the TSMC 0.18mum CMOS process. Its power consumption is 1.8mW

1.5-V Linear CMOS OTA with -60dB IM3 for High Frequency Applications

A novel configuration of linearized Operational Transconductance Amplifier (OTA) for low-voltage and high frequency applications is proposed. By using double differential pairs and the source degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability, and thus reduces distortion caused by common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60dB third-order inter- modulation (IM3) distortion for up to 0.9 VPP at 40 MHz. Ths OTA was fabricated by the TSMC 180-nm Deep N-WELL CMOS process. It occupies a small area of 15.1 x 10-3 mm2 and the power consumption is 9.5 mW under a 1.5-V supply voltage.

A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold Operation

A low power CMOS voltage reference circuit was designed and implemented by TSMC 0.18-mum CMOS process. The voltage reference circuit uses the VGS difference between two MOSFETs operating in the weak-inversion region to generate the voltage with positive temperature coefficient. The reference voltage can be obtained by combining the weighted VGS difference with weak-inversion VGS voltage, which has a negative temperature coefficient. This circuit provides a nominal reference voltage of 621 mV, a temperature coefficient of 11.5 ppm/degC in [-20degC~120degC] from a 1.5 V supply voltage. The line regulation of the reference voltage is 6 mV/V when the supply voltage is increased from 1.5 V to 3 V. The chip area is 0.132 mm2 and dissipates 17.25 muW at room temperature. By connecting a 0.22 muF loading capacitor, the measured noise density at 100 Hz and 100 kHz is 0.14 muV/radicHz and 22.2 muV/radicHz, respectively.

A High Speed Pseudo-Differential OTA with Mobility Compensation Technique in 1-V Power Supply Voltage

This paper presents a high linearity operational transconductance amplifier (OTA) based on pseudo-differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down to achieve high speed operation. Transconductance tuning could be achieved by a MOS operating in the linear region. The OTA fabricated in the TSMC 0.18-mum CMOS process occupies a small area of 4.5 times 10-3 mm2. The measured third-order inter-modulation (IM3) distortion under 1-V power supply voltage remains below -52 dB up to 50 MHz for a 400 mV pp differential input. The static power consumption is 2.5 mW. Experimental results demonstrate the agreement with theoretical analyses.

1-V Linear CMOS Transconductor with -65 dB THD in Nano-Scale CMOS Technology

This paper presents a high linearity MOSFET-only transconductor based on differential structures. The linearity is improved by mobility compensation techniques as the device size is scaled down in the nano-scale CMOS technology. Transconductance tuning could be achieved by transistors operating in the linear region. The simulated total harmonic distortion (THD) under 1-V power supply voltage shows 12 dB improvement of the proposed version, and -65 dB THD can be achieved for a 1 MHz 700 mVpp differential input. Monte-Carlo simulation over the corner variation and transistor mismatch guarantees the shown performance. The static power consumption is 130 muW. Simulation results demonstrate the agreement with theoretical analyses.

1-V 365-

This paper presents a novel 1-V 2.5-MHz continuous-time filter for 3G wireless application, fabricated using a standard 55-nm CMOS process. The four-pole filter topology includes a single pole-tracking Operational Amplifier (OPAMP) structure to achieve low in-band noise levels, high out-of-band linearity, and reduced power consumption. An automatic frequency tuning circuit is developed to compensate for process and environmental variations. The proposed filter achieves inband noise of 18-μV rms and out-of-band IIP3 of 33 dBm within 365 μW. The out-of-band spurious-free dynamic range is measured at 76.7 dB, resulting in a figure-of-merit of 1.24 × 10-4 fJ.

\mu{\rm W}

A CMOS fourth-order linear phase low-pass filter used for high speed wireless/wireline system is realized in 0.18-µm CMOS process. The high speed filter is designed based on operational transconductance amplifier (OTA) biquad sections. As well known, large transconductance is required for high speed applications, and thus the conventional source degeneration topology, which operates with the trade-off of linearity and transconductance, is not suitable. In this paper, the proposed OTA use the negative current feedback topology to maintain linearity for high speed application. By using the proposed OTA as a building block, a 4-th order low-pass filter is realized. Fabricating in 0.18-µm CMOS technology, the −3dB filter frequency response at 250MHz is measured. The measured HD3 performance is about −40dB and the group delay variation is less than 5ns at the filter −3dB cutoff frequency.