Chung-k Seo

Comparison of electrical and optical interconnect

In this paper, we present a comparison between electrical and optical interconnect for chip-techip signaling in terms of data rate and system power consumption on FR4 circuit boards. The results show that optical interconnection is the only functional technology for a single serial line of 20cm length at a lOGbps data rate. Low power CMOS logic driving parallel unterminated copper interconnect on FR4 substrates should be replaced by terminated transmission lines at lOcm lengths for lOGbps aggregate throughput and at 20cm for IGbps aggregate throughput. Terminated copper transmission line interconnect on FR4 substrates can achieve lOGbps per line operation at 20“ provided no vias are used in the interconnect, or via technology with low reflection loss is developed. With vias, terminated copper transmission line interconnect must be replaced at 20cm for lOGbps per he, however, 4 parallel terminated transmission lines with vias each running at 2.5Gbps can achieve lOGbps aggregate communication over a 20cm length. Thus, serial optics should only be used to replace 4 parallel electrical transmission lines if the power dissipation of the optical driver circuitry is less than 4 times the 2.5Ghps electrical driver power consumption. For electrical interconnect, two interconnection technologies were studied. We first technology uses ideal sources to drive a single serial terminated 500 copper transmission line on FR4 both with and without vias. The second technology uses conventioinal CMOS digital interface circuits and parallel unterminated, 50R transmission line interconnect of width 16,32, and 64bits made from copper on an FR4 substrate. These two technologies represent low power CMOS and the ultimate limit of FR4 copper traces for unequalied digital signaling. For optical interconnect, commercial SiGe optoelectronic laser driver circuit technology and published optical waveguide data were used to determine performance limits. Compliance with the IEEE 802.3ae XAUI interface eye mask was used to determine acceptable data transmission in all cases.

A CAD tool for system-on-chip placement and routing with free-space optical interconnect

A wiring model for system-on-chips utilizing flexible free space optical interconnects is introduced In this paper, we develop a CAD tool for physical placement of modules in system-on-chips manufactured using the optical interconnect technology. The tool also determines which of the interconnect are routed electrically and which are routed optically without exceeding the routing capacity of the optical interconnect while minimizing electrical wire length. About 50% reduction in largest delay of electrical wires is obtained through the use of optical interconnect (Performance improvement by a factor of 2).

Physical design of optoelectronic system-on-a-package: a CAD tool and algorithms

We propose a new approach to the physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnect technology. The objective is to improve the performance of SOP by replacing long distance electrical interconnects with optical waveguide interconnects. A new simultaneous optimization algorithm for module placement and routing of electrical and optical interconnects is introduced. It not only improves the performance of SOP, but reduces the simulation time. Even though a small portion of electrical interconnects are replaced with optical interconnects, more than 21% improvement of the SOP performance is achieved.

Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages

A new approach to optical clock distribution utilizing optical waveguide interconnect technology is introduced. In this paper, we develop a new algorithm for design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. The optimization approach takes into account bending and propagation losses of optical waveguides. Less than 26.1psec in signal timing skew is obtained for a signal flight time of 614.38psec. About 15% reduction in optical power consumption is also obtained over clock nets routed with existing (optical) methods.

Physical design of optoelectronic system-on-a-package using optical waveguide interconnects

In this paper, we develop a computer-aided design (CAD) tool for physical design of optoelectronic system-on-a-package (SOP) using optical waveguide interconnects. The tool assigns the optimal location to modules and replaces long electrical interconnects with optical waveguide interconnects in order to maximize the overall performance of the optoelectronic system-on-a-package. More than 47% improvement in system-on-a-package performance is obtained through the use of optical waveguide interconnects.

Free-space optical interconnect for high-performance MCM systems

An efficient co-optimization algorithm of placement and routing for high-performance multichip module (MCM) systems utilizing free-space optical interconnect technology is introduced. A computer-aided design (CAD) tool is developed for optimizing placement of modules and routing of electro-optic interconnects simultaneously without exceeding the routing capacity of the optical interconnect. About 48% saving in total routing cost is achieved through the use of 600 optical interconnects with 100 modules. It translates to doubling of the MCM performance.

Wiring optimization for propagation delay and reduced power consumption in multichip modules with free-space optical interconnect

In this paper, we develop “GOETHE (Generic OptoElectronic system design THEurgist), a computer-aided design (CAD) tool for physical placement and routing in multichip modules (MCMs) manufactured using free-space optical interconnect technology. GOETHE determines the optimal module placement with the minimum propagation delay without exceeding the routing capacity of the optical substrate while reducing power consumption. More than 62% reduction in propagation delay and more than 21% reduction in power consumption is obtained through the use of freespace optical interconnect. It tiims out that chip speed can be improved by a factor of 1.5 (with less power consumption) compared to MCMs with only electrical interconnections.