Chung-Yen Chien

Precise Ge quantum dot placement for quantum tunneling devices

This study demonstrates the precise placement of Ge quantum dots (QDs) in an SiO2 or Si3N4 matrix in a self-organized manner by thermally oxidizing SiGe in nanostructures. The effectiveness of this method is shown by a variety of geometries including nanotrenches, nanorods and polygonal nanocavities. Modulating the structural geometry and peripheral spacer materials effectively places a single Ge QD in the center of an oxidized SiGe nanostructure or individual QDs at the corners (edges). This study also reports the fabrication of Ge QD single-electron devices that exhibit clear Coulomb staircases and differential conductance oscillations at room temperature.

Matrix and quantum confinement effects on optical and thermal properties of Ge quantum dots

The influence of SiO_2 and Si_3N_4 dielectric matrices on the structural, phonon, luminescence and thermal properties of Ge quantum dots (QDs) has been experimentally investigated. Compared with the case of QDs in SiO_2 layers, Si_3N_4 matrix imposes large interfacial surface energy on QDs and enhances their Ostwald ripening rate, appearing to be conducive for an improvement in crystallinity and a morphology change to a more perfectly spherical shape of Ge QDs. Quantum confinement induced electronic structure modulation for Ge QDs is observed to be strongly influenced not only by the QD size but also by the embedded matrix. Both matrix and surface effects offer additional mechanisms to QD itself for controlling the optical and thermal properties of the QDs.

Nanoscale, Catalytically Enhanced Local Oxidation of Silicon-containing Layers by 'Burrowing' Ge Quantum Dots

A new phenomenon of highly localized, nanoscale oxidation of silicon-containing layers has been observed. The localized oxidation enhancement observed in both Si and Si(3)N(4) layers appears to be catalyzed by the migration of Ge quantum dots (QDs). The sizes, morphology, and distribution of the Ge QDs are influenced by the oxidation of the Si-bearing layers. A two-step mechanism of dissolution of Si within the Ge QDs prior to oxidation is proposed.

Formation of Ge quantum dots array in layer-cake technique for advanced photovoltaics.

We report a simple and manageable growth method for placing dense three-dimensional Ge quantum dot (QD) arrays in a uniform or a graded size distribution, based on thermally oxidizing stacked poly-SiGe in a layer-cake technique. The QD size and spatial density in each stack can be modulated by conditions of the Ge content in poly-Si(1-x)Ge(x), oxidation, and the underlay buffer layer. Size-dependent internal structure, strain, and photoluminescence properties of Ge QDs are systematically investigated. Optimization of the processing conditions could be carried out for producing dense Ge QD arrays to maximize photovoltaic efficiency.

Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO2/InAs pMOS Capacitors

Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator semiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive X-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the formation of interfacial oxide, TiO2, between the Ti gate and HfO2 gate dielectric layer, enhancing the gate modulation on the surface potential of InAs. An in situ HfO2 deposition onto the n-InAs channel with an interfacial layer (IL) of one-monolayer InP followed by a 300°C post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level pinning, which is evidenced by the distinct capacitance dips in the high-/low-frequency C-V characteristics. The interface trap states could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction and a steep voltage-dependent depletion capacitance.

Formation of 3D Ge quantum dots array for advanced photovolatics in layer-cake technique

Placement of quantum dots (QDs) and insight into QDs basic internal structure and optical properties lay nature cornerstones for advanced photonic devices. We report a manageable growth method for placing dense three-dimensional Ge QD arrays in a uniform or a grading size distribution, using thermal oxidation of poly-SiGe in layer-cake techniques. The QD size and spatial density in each stack could be well modulated by Ge content in poly-Si1−xGex, oxidation and underlay buffer layer conditions. Size-dependent internal structure, strain, and photoluminesce properties of Ge QDs are systematically investigated. Optimization of processing conditions was carried out for producing dense Ge QD arrays for maximizing photovoltaic efficiency.

Designer Ge quantum-dot phototransistors for highly-integrated, broadband optical interconnects

We report high-responsivity Ge quantum dots (QDs) MOS phototransistors as on-chip transducers for highly-integrated, broadband Si-based optical interconnects. Self-organized heterostructure of Ge-QD/SiO2/Si-channel is fabricated in a single step through selective oxidation of SiGe nano-pillars over a Si3N4 buffer layer on Si substrates. Dark current densities (10-7A/mm2), photocurrent-to-dark current ratio (~ 107) and photoresponsivities (>10 A/W), external quantum efficiency (~240%), and response time (1.4ns) are measured on the Ge-QD phototransistors under 850 nm illumination. Detection wavelength is tunable from near infrared to near ultraviolet by reducing the QD size from 90 to 7 nm, and the optimal photoresponsivity is tailored by the QD size and effective thickness of gate dielectrics.

Size tunable Ge quantum dot phototrasnsistors for optical interconnects with high figure of merits

We report a unique, CMOS approach for the inclusion of size-tunable (7-50-nm), spherical Ge quantum dots (QDs) into gate stacks of Si MOS transistors, through selective oxidation of SiGe pillars over the buffer layer of Si3N4 on top of the Si substrate. The Ge-QD MOS phototransistors feature extremely low dark current densities (Ioff ~ 0.27 pA/μm2), high Ion/Ioff (>106), steep subthreshold swing (~175 mV/dec at 300 K), superior external quantum efficiency (~240%), and fast response time of 1.4ns under illumination of 850 nm, providing a core building block for high-performance Ge optical transducers for on-chip optical switches and transducers for Si-based optical interconnect applications. Most importantly, the detection wavelength of the Ge QD is tunable from near infrared to near ultraviolet by reducing the QD size from 50 to 7 nm, and the optimal photoresponsivity is tailored by the Ge QD size and the effective thickness of gate dielectrics.

Positioning and numbering Ge quantum dots for effective quantum electrodynamic devices

Department of Electrical Engineering, National Central University,ChungLi, Taiwan, ROC, 32001 Phone: +886-3-422-7151 ext.34465 FAX:+886-3-425-5830 E-mail: pwli@ee. ncu.edu.tw