Chung-Yuan Lee

A novel trench capacitor enhancement approach by selective liquid-phase deposition

For the first time, a novel and simple trench bottle integrated process is demonstrated on dynamic random access memory (DRAM) manufacturing by selective liquid phase deposition (S-LPD) oxide. After photoresist (PR) filled into a deep trench (DT) and was recess etched at around 1.3 /spl mu/m depth, LPD oxide can be selected as a deposit onto the DT sidewall but not as a deposit on the PR surface. This S-LPD oxide is formed by using hexa-fluosilic acid (H/sub 2/SiF/sub 6/) and water without H/sub 3/BO/sub 3/. After the PR is removed, the LPD oxide becomes a protective layer on DT upper portion. Thus, the DT bottom area can be enlarged to form a trench bottle by NH/sub 4/OH wet etching. Compared to conventional DT trench, 20% of capacitance was enhanced by this S-LPD process. This novel and low-cost method is for the first time demonstrated on 200-mm wafer 110-nm trench DRAM technology.

Evidence of Zero Potential Spike Energy in AlGaAs/GaAs Heterostructure Emitter Bipolar Transistors

The potential spike energy at the emitter junction of AlGaAs/GaAs heterostructure emitter bipolar transistors (HEBT) was directly measured for the first time. Experimental data revealed that emitter thickness as thin as 300 A is thick enough to eliminate potential spike without compositional grading. It is found that the band bending in n-GaAs reduces the potential spike and hence very low offset voltage of 70 mV with high current gain of 150 can be obtained.

Gate-Induced Drain Leakage (GIDL) Improvement for Millisecond Flash Anneal (MFLA) in DRAM Application

In this paper, we successfully demonstrated gate-induced drain leakage (GIDL) improvements by millisecond flash anneal (MFLA) on a DRAM product. Fundamental studies on blanket wafers and the device characteristics of product wafers showed positive results. These proved that MLFA has good potential for DRAM application. The periphery NMOS off current was reduced by 36%. This off-current improvement reduced the standby current by 5% in a DRAM functional test. The GIDL reductions for an NMOS array and periphery N- and PMOSs were 14.5%, 15%, and 39%, respectively. A model for GIDL improvement by MFLA application to DRAM production was proposed. It is believed that the main GIDL-impacted factor was the high electric field caused by defect-assisted tunneling and junction profile abruptness under the gate edge. Bright field and weak-beam dark-field TEM images showed perfect dislocation loops and fault dislocation loops staying in the {113} plane with a size of around 17 x 20 nm in the junction area. These defects could be one of the leakage sources for a defect-assisted trap charge, leading to trap-assisted tunneling.

DRAM Data Retention and Cell Transistor Threshold Voltage Reliability Improved by Passivation Annealing Prior to the Deposition of Plasma Nitride Layer

We report, for the first time, that the fail bit counts of dynamic random access memory (DRAM) reduced by 18% and the yield loss after packaging induced by data retention degradation decreased by 1.16% for a trench DRAM cell; this reduction was attributed to a change in the process position of passivation annealing. Moreover, the cell transistor threshold voltage (CTVth) shift was reduced to 53 mV, and the uniformity of the CTVth was improved from 100 to 38 mV; this provided the DRAM cell with a large margin for further reducing both the dose of the threshold implant and the electrical field. We proposed a possible mechanism of carrying out passivation annealing prior to the deposition of a plasma nitride layer in order to increase the supply of hydrogen for the passivation of the crystalline defects as well as improving data retention. The CTVth was increased by breaking of weak Si-H bonds by plasma charging during the deposition of the plasma nitride layer. Data retention degradation after the packaging process ( ~ 250°C) reduced because of the presence of a number of strong Si-H bonds, indicating the presence of a greater number of interface trap states near the storage trench than near the bit line, as observed in the case when hot-carrier stress was applied under two conditions. Results of data retention analysis show that the fail bit counts are primarily influenced by the junction leakage current and not the gate-induced drain leakage current. Above observation is dependent on device process flow, which provided us an easy way for DRAM device optimization and maximized manufacturing process window.

Dependence of DRAM Device Performance on Passivation Annealing Position in Trench and Stack Structures for Manufacturing Optimization

The dependence of dynamic random access memory (DRAM) device performance on trench and stack cell structures was first observed by changing the process position of passivation annealing. For the trench DRAM, the data retention fail bit counts (FBCs) decreased by 18% and the cell transistor threshold voltage (CTVth) shift by 53 mV. The FBCs are primarily influenced by the junction leakage current. In contrast, for the stack DRAM, the data retention FBCs increased by 225% and the CTVth shift increased by 20 mV. The FBCs are primarily influenced by the gate-induced drain leakage (GIDL) current because of the large gate and the drain overlap region in the recess channel array transistor (RCAT). The interface states increased after the deposition of the plasma nitride layer, as observed in the charge pumping measurement in the trench DRAM. Transmission electron microscopy indicated that the gate oxide thickness in the bottom region of the RCAT is thinner to generate gate oxide leakage. Furthermore, a decrease in the activation energy from 0.64 to 0.55 eV implies the occurrence of GIDL current, which corresponds to the FBC analysis result. This paper demonstrated that the passivation annealing position requires careful adjustment for device and manufacturing optimization.

In-Line Supermapping of Storage Capacitor for Advanced Stack DRAM Reliability

Model-based infrared reflectometry (MBIR) is a novel nondestructive technology which has been introduced for fast-response in-line monitoring of deep-trench dynamic random access memory (DRAM). However, for mainstream stack DRAM, MBIR application is hard to implement due to underlayer metal reflection noise. Furthermore, the production control of the stack DRAM storage capacitor is always the major concern of yield loss and reliability problems. Traditionally, the production monitoring of the storage capacitor has been performed by an x-sectional scanning electron microscope in a PFA laboratory or electron beam inspection (EBI). Unfortunately, it is quite time consuming and has a high cost. In this paper, we report a successful MBIR measurement at scribing line scatter spot with void fraction analysis methodology on 50-nm stack DRAM. We demonstrate excellent correlation of the electrical storage capacitance with a special donut shape, the EBI of underetched storage contact, and the neighboring storage capacitor shortage. The repeatability of the MBIR test is good with average sigma values of 0.56% for the top void fraction and 1.73% for the bottom void fraction, which indicate that MBIR can become a powerful metrological tool for improving product yield and reliability.

Residual Clamping Force and Dynamic Random Access Memory Data Retention Improved by Gate Tungsten Etch Dechucking Condition in a Bipolar Electrostatic Chuck

It was found that the residual clamping force of bipolar electrostatic chucks created by the residual charge between a wafer and an electrode would not only cause a wafer sticking problem but also degrade dynamic random access memory (DRAM) data retention performance. The residual clamping force and data retention fail bit count (FBC) of DRAM showed strong correlations to the gate tungsten etch dechucking process condition. Wafer sticking only degraded DRAM cell retention performance, and did not influence any in-line measurement or electrical parameters. Electrical characterization analysis of the FBC proved that the retention loss was mainly due to junction leakage rather than gate-induced-drain-leakage current. A new approach was proposed to suppress this leakage by introducing N2 gas instead of O2 to supply more plasma charges for neutralizing the wafer surface residual charges. The wafer shift dynamic alignment (DA) offset and retention FBC could be reduced by 50 and 40%, respectively. Poor data retention was suspected because of the compressive stress caused by wafer sticking DA shift resulting in a high electric field at the junction and an increase in junction leakage at the storage node.

Integration of Millisecond Flash Anneal on CMOS Devices for DRAM Manufacturing

We successfully demonstrate the millisecond flash anneal (MFLA) on a matured DRAM product. The GIDL improvements for array NMOS, periphery N and P MOS are 14.5%,15%, and 39% respectively. The mechanisms of GIDL impact at different process stages have been reviewed. With MFLA replacement, N and PMOS on-current (Ion) gains 4.3% and 11.8% respectively. Superior off current (Ioff) reduction for periphery N and PMOS reach 150% and 500% respectively. Vt roll- off, Vt-Ion, Ion-Ioff correlation, overlap capacitance, and drain induced barrier lowering (DIBL) have been reviewed. TEM data show poly grain enlargement and clustering defects staying at different junction depths. This study shows that MFLA has the benefit for lower thermal budget, high dopant activation, and shallow junction for sub-50 nm DRAM.

Full Range Work Function Modulation by Nitrogen Incorporation in Hf-Mo Binary Alloys Gate Electrode

in Hf–Mo Binary Alloys Gate Electrode Chao-Sung Lai, Chin-Wei Huang, Hsing-Kan Peng, Chih-Hsin Chen Yu-Ching Fang, Li Hsu, Hui-Chun Wang, Chung-Yuan Lee, Shian-Jyh Lin Department of Electronic Engineering, Chang Gung University, 259 Wen-Hwa 1 Road, Kwei-Shan Tao-Yuan 333, Taiwan Chung-Shan Institute of Science & Technology Materials & Electro-Optics Research Division 32500, Lung-Tan, Taoyuan, Taiwan 3 Nanya Technology Corporation, Hwa-Ya Technology Park, 669 Fu-Hsing 3rd Rd, Kueishan, Taoyuan, Taiwan Phone: +886-3-2118800 ext. 5786 E-mail: cslai@mail.cgu.edu.tw

Fluorinated ALD Al/sub 2/O/sub 3/ Gate Dielectrics by CF/sub 4/ Plasma

Introduction As device scaling down, the silicon oxide thickness is shrinking to nanometer scale. High-k dielectric is necessary to avoid high gate leakage current and enhance drive ability. Al2O3 is a candidate dielectric for DRAM or CMOS technology because of its high thermal stability and energy band gap [1, 2]. However, some fixed charges are located in the Al2O3 films and affects the flatband voltage (Vfb) shift. CF4 plasma had been used in the HfO2 gate dielectric to improve hysteresis [3]. In this study, a novel approach for fluorinated ALD-Al2O3 films by the CF4 plasma was proposed. Due to fluorine incorporation, the characterization was improved including breakdown field, hysteresis and reliability. Experiment Rapid thermal nitridation (RTN) was processed on p-Si followed by atomic layer deposition (ALD)-Al2O3 with precursor of Trimethylaluminum (TMA) and O3. ALD processes were split to 40, 69 and 109 cycles. CF4 plasma was treated on the Al2O3 for 1, 3 and 5 min. Aluminum gate electrode was deposited and patterned. The key processes for (a) without CF4 plasma and (b) with CF4 plasma are shown in the Fig. 1. Electrical characteristics were measured with gate areas of 80μm*80μm. Results and Discussion