Chunghee Kim

A performance-driven logic emulation system: FPGA network design and performance-driven partitioning

FPGAs are widely used for logic emulation, software acceleration, custom computing, and prototyping. The architecture (or the interconnect mechanism of a FPGA network) of an emulator has profound effect on the performance (speed) and efficiency (chip utilization) of the emulator. In this paper, several architectures of FPGA networks are suggested, and they are compared with other typical existing architectures by using the MCNC partition benchmark circuits. Experimental results show that tripartite network outperforms six other typical architectures both in performance and in efficiency. For this study, the propagation delay of a path is estimated by the number of hops (interchip connections) and the number of intrachip connections on the path, and thus it is independent of a specific FPGA type. To partition a given circuit into the given prerouted network of FPGAs, a new routability-driven partitioning algorithm is developed. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average, and that performance-driven partitioning is effective in reducing critical time delays.

Performance-driven circuit partitioning for prototyping by using multiple FPGA chips

A new performance-driven partitioning algorithm has been developed to implement a large circuit by using multiple FPGA chips. Partitioning for multiple FPGAs has several constraints to satisfy so that each partitioned subcircuit can be implemented in a FPGA chip. To obtain satisfactory results under the constraints, the partitioning is performed in two phases which are the initial partitioning for global optimisation and the iterative partitioning improvements for constraint satisfaction. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average and that performance-driven partitioning is effective in reducing critical time delays.

A combined hierarchical placement algorithm

A hierarchical placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimize the number of crossing nets while the objective of placement by simulated annealing is usually to minimize the total estimated wire-length. The combined placement algorithm can optimize both the routing density and the estimated wire-length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction, i.e., big groups of cells are placed at the beginning and leafcells are placed at the final level. Several standard-cell and sea-of-gates circuits are placed using the combined placement techniques and promising results are obtained when compared with those of several other placement methods.

An improved partitioning method using clustering refinement [VLSI design]

Partitioning is an important step in the hierarchical design of very large scale integrated circuits. In this research, an improved partitioning based on 2-level hierarchy has been developed. New techniques for clustering and cluster refining have been developed. After clusters are formed, they can be refined by moving cells among the clusters. For partitioning, the hierarchical gradual constraint enforcing partitioning method has been used. The clustering-based partitioning algorithm has been applied to MCNC benchmark examples and produced excellent results.