Wonchan Kim

An experimental high-density DRAM cell with a built-in gain stage

A new high-density DRAM cell concept is proposed and experimentally demonstrated. This cell, composed of two transistors and one capacitor, generates a large bit line signal with a small cell capacitance during the read cycle. Since it does not need a large storage capacitance and one transistor is stacked on the top of the other transistor, the cell size is small and can be easily scaled down for future generations of memory devices. The unit cell size fabricated using a 4 M SRAM process without any process modification is 1.8 /spl mu/m/spl times/2.85 /spl mu/m. The proposed cell can be adopted to store multi-bit information. The fabricated prototype cell shows a resolution of about 3.5 bit. >

Exponential curvature-compensated BiCMOS bandgap references

An exponential curvature compensation technique for bandgap references (BGRs) which exploits the temperature characteristics of the current gain /spl beta/ of a bipolar transistor is described. This technique requires no additional circuits for the curvature compensation; only a size adjustment of a bias transistor in a conventional first-order compensated BGR is required. Positive and negative versions of the exponential curvature-compensated BGR have been fabricated using a 1.5 /spl mu/m BiCMOS process. Average temperature coefficients (TCs) of the negative BGR are measured as 2.4 and 6.7 ppm//spl deg/C, and those of the positive BGR are measured as 3.5 and 8.9 ppm//spl deg/C over the commercial (0/spl sim/70/spl deg/C) and military (-55/spl sim/125/spl deg/C) temperature ranges, respectively. These circuits dissipate 0.37 mW with a single 5 V supply, and occupy 270/spl times/150 /spl mu/m/sup 2/ and 290/spl times/150 /spl mu/m/sup 2/, respectively. >

A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops

A 1.2 GHz dual-modulus prescaler IC fabricated with 0.8 /spl mu/m CMOS technology is presented in this paper. The dual-modulus prescaler includes a synchronous counter (divide-by-4/5) and an asynchronous counter (divide-by-32). A new dynamic D-flip-flop (DFF) is developed for the high-speed synchronous counter. The maximum operating frequency of 1.22 GHz with power consumption of 25.5 mW has been measured at 5 V supply voltage.

A 600-dpi capacitive fingerprint sensor chip and image-synthesis technique

This paper examines the possibility of a low-cost, high-resolution fingerprint sensor chip. The test chip is composed of 64/spl times/256 sensing cells (chip size: 2.7/spl times/10.8 mm/sup 2/). A new detection circuit of charge sharing is proposed, which eliminates the influences of internal parasitic capacitances. Thus, the reduced sensing-capacitor size enables a high resolution of 600 dpi, even using a conventional 0.6 /spl mu/m CMOS process. The partial fingerprint images captured are synthesized into a full fingerprint image with an image-synthesis algorithm. The problems and possibilities of this image-synthesis technique are also analyzed and discussed.

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systems

This paper presents the design of a fully-integrated CMOS frequency synthesizer for PCS- and cellular-CDMA wireless systems. The proposed charge-averaging charge pump scheme suppresses fractional spurs and the VCO combined with coarse tuning improves phase noise characteristics. The improved architecture of the dual-path loop filter makes it possible to implement a large time constant on a chip. Fabricated in 0.35-/spl mu/m CMOS technology, this circuit provides 10 kHz channel spacing with phase noise of -106 dBc/Hz at 100 kHz offset. Power dissipation is 60 mW with 3.0 V supply.

A dual-loop delay-locked loop using multiple voltage-controlled delay lines

This paper describes a dual-loop delay-locked loop (DLL) which overcomes the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). A reference loop generates quadrature clocks, which are then delayed with controllable amounts by four VCDLs and multiplexed to generate the output clock in a main loop. This architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. The DLL incorporates a replica biasing circuit for low-jitter characteristics and a duty cycle corrector immune to prevalent process mismatches. A test chip has been fabricated using a 0.25-/spl mu/m CMOS process. At 400 MHz, the peak-to-peak jitter with a quiet 2.5-V supply is 54 ps, and the supply-noise sensitivity is 0.32 ps/mV.

A low-voltage, low-power CMOS delay element

A low voltage, low power CMOS delay element is proposed. With unit CMOS inverter load, the delay from 2ns to 10¿s is achieved with the power consumption less than 30pW/MHz in 0.8¿m CMOS technology. Based on the CMOS thyristor concept, the delay value of the proposed element can be designed in a wide range with the control current. The designed delay value is less sensitive to the supply voltage variation and temperature than those of RC or CMOS inverter based delay elements.

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiver

This paper presents a full-CMOS transmitter and receiver for 2.0-GHz wide-band code division multiple access with direct conversion mixers and a DC-offset cancellation scheme. The direct conversion scheme combined with a multiphase sampling fractional-N prescaler alleviates the problems of the direct conversion transmitter and receiver. Digital gain control is merged into the baseband filters and variable-gain amplifiers to optimize the linearity of the system, reduce the noise, and improve the sensitivity. Variable-gain amplifiers with DC-offset cancellation loop eliminate the DC-offset in each stage. The chip implemented in 0.35-/spl mu/m CMOS technology shows the experimental results of 6 dBm maximum output power with 38-dB adjacent channel power rejection ratio at 1.92 MHz, 50-dB dynamic range, and 363-mW power consumption in the transmitter. The receiver shows -115.4 dBm sensitivity, a 4.0-dB noise figure, and a dynamic range of 80-dB with 396-mW power consumption.

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit

A variable-interval oversampling clock/data recovery circuit (CDR) provides robust operation under varying jitter conditions. An eye-measuring loop in the CDR enables data recovery at maximum eye-opening, responding to the amount and shape of jitter. The CDR in 0.25 /spl mu/m CMOS shows <10/sup -13/ BER for 2/sup 7/-1 PRBS (pseudo-random-bit-sequence) at 5GBaud.

A 50% power reduction scheme for CMOS relaxation oscillator

In this paper, a CMOS relaxation oscillator is presented. The proposed oscillator has only one tail current source unlike the emitter coupled multivibrator. All the tail current flows through the timing capacitor and thus the charging slope of the timing capacitor is doubled. This enhances the operating speed without increasing the power consumption. The oscillator is fabricated in a standard 0.8 /spl mu/m CMOS process. The maximum operating frequency is 923 MHz at a 3.3 V single supply, while the oscillator draws 6 mA.