Hyungcheol Shin

Three-Dimensional nand Flash Architecture Design Based on Single-Crystalline STacked ARray

Various critical issues related with 3-D stacked nand Flash memory are examined in this paper. Our single-crystalline STacked ARray (STAR) has many advantages such as better scalability, possibility of single-crystal channel, less sensitivity to 3-D interference, stable virtual source/drain characteristic, and more extendability over other stacked structures. With STAR, we proposed a unit 3-D structure, i.e., “building.” Then, using this new component, 3-D block and full chip architecture are successfully designed. For the first time, the structure and operation methods of the “full” array are considered. The fully designed 3-D nand Flash architecture will be the novel solution of reliable 3-D stacked nand Flash memory for terabit density.

A simple wide-band on-chip inductor model for silicon-based RF ICs

In this paper, we developed a simple wide-band inductor model that contains lateral substrate resistance and capacitance to model the decrease in the series resistance at high frequencies related to lateral coupling through the silicon substrate. The model accurately predicts the equivalent series resistance and inductance over a wide-frequency range. Since it has frequency-independent elements, the proposed model can be easily integrated in SPICE-compatible simulators. The proposed model has been verified with measured results of inductors fabricated in a 0.18-/spl mu/m six-metal CMOS process. We also demonstrate the validity of the proposed model for shielded inductors. The proposed model shows excellent agreement with measured data over the whole frequency range.

Thin oxide charging current during plasma etching of aluminum

CV measurement is shown to be a more sensitive technique for characterizing plasma-etching induced damage than oxide breakdown. Plasma etching of Al is shown to produce severe distortions in the oxide CV characteristics, from which one can easily deduce the plasma charging current over many orders of magnitude. A clear radial variation of stressing is found and the charging current increases in proportion to the Al peripheral length rather than the area. Using the measured 10-pA/ mu m of the charging current, one should be able to predict the impact of this etch process on oxide integrity and interface stability for a given antenna geometry.<<ETX>>

A simple and analytical parameter-extraction method of a microwave MOSFET

A simple and accurate parameter-extraction method of a high-frequency small-signal MOSFET model including the substrate-related parameters and nonreciprocal capacitors is proposed. Direct extraction of each parameter using a linear regression approach is performed by Y-parameter analysis on the proposed equivalent circuit of the MOSFET for high-frequency operation. The extracted results are physically meaningful and good agreement has been obtained between the simulation results of the equivalent circuit and measured data without any optimization. Also, the extracted parameters, such as g/sub m/ and g/sub ds/, match very well with those obtained by DC measurement.

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.

Thin oxide damage by plasma etching and ashing processes

In the study reported, the plasma Al etching and resist ashing processes caused Fowler-Nordheim current to flow through the oxide. The stress current was collected only through the aluminum surfaces not covered by the photoresist during the plasma processes. The plasma stress current was proportional to the Al pad peripheral length during Al etching and the Al pad area during photoresist stripping. Using the measured stress current, the breakdown voltage distribution of oxides after plasma processes can be predicted accurately. A model of oxide damage due to plasma etching is proposed.<<ETX>>

A New Capacitorless 1T DRAM Cell: Surrounding Gate MOSFET With Vertical Channel (SGVC Cell)

We propose a surrounding gate MOSFET with vertical channel (SGVC cell) as a 1T DRAM cell. To confirm the memory operation of the SGVC cell, we simulated its memory effect and fabricated the highly scalable SGVC cell. According to simulation and measurement results, the SGVC cell can operate as a 1T DRAM having a sufficiently large sensing margin. Also, due to its vertical channel structure and common source architecture, it can readily be made into a 4F2 cell array

Modeling oxide thickness dependence of charging damage by plasma processing

Develops a quantitative model for thin oxide plasma charging damage by examining the oxide thickness dependence of charging current. The current is deduced from capacitance-voltage (CV) curves of metal-oxide-semiconductor (MOS) capacitors after plasma etch. The model predicts the oxide thickness dependence of plasma charging successfully. It is shown that plasma acting on a very thin oxide during processing may be modeled as essentially a current source. Thus the damage will not be greatly exacerbated as oxide thickness is further reduced in the future. Gate oxide breakdown voltage distribution of MOS capacitors after plasma processing can be predicted accurately from that of a control wafer by using a defect-induced breakdown model.<<ETX>>

Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory

In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.

A simple parameter extraction method of spiral on-chip inductors

Accurate measurement and parameter extraction for spiral inductors are very important in monolithic microwave integrated circuit (MMIC) design. In this paper, we have proposed an easy and simple model parameter extraction method of wide-band on-chip inductor. The simple extraction methodology is applied to extract parameters from the measured S-parameters of spiral inductors fabricated with 0.18-/spl mu/m CMOS technology. Model prediction shows excellent agreement with the measured data over a wide frequency region. Also, the model can be easily integrated in SPICE-compatible simulators because all the elements are frequency independent. This method will provide practical and useful circuit parameters for MMIC design.