Chunhua Qi

Impact of BTI aging effect on soft error rate of combination circuit

Aging and soft errors have become the two most critical reliability issues for nano-scale CMOS circuit. First, in this paper, the aging effect due to bias temperature instability (BTI) is analyzed on different logic gate using 45nm Technology, and simulated the critical charge and delay which can influence soft error rate (SER) result. Second, a method of SER calculation considering BTI effect is given. As a result, we find that the effect of PBTI on the circuit is less than that of NBTI on the critical charge. The critical charge and delay affect the masking effect and the probability of an error in SER calculation. Experimental result shows that the SER calculation considering BTI effect is feasible and the impact of BTI on benchmark circuits SER is up to 21.6%.

Design of Single-Event Tolerant Latches in 65nm CMOS Technology for Enhanced Scan Delay Testing

Nowadays, single event upsets (SEU) and the occurrence of delay faults caused by manufacturing defects are significant problems in high density VLSIs. Thus, researchers have drawn great attention on SEU tolerant design and delay fault testing. In this paper, two novel slave latches and a master latch have been proposed to improve the SEU tolerance of a flipflop in scan delay testing. The main purpose of this design is to solve the problems appearing in previous state-of-the-art latches. Simulation results show that, the two proposed slave latches can tolerate particles with charges of more than 1 pC. Furthermore, areas, CK-Q delay and power consumption are also investigated and made comparisons with recent state-of-the-art latches.

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs

In recent years, SRAM-based FPGAs have been applied in space due to its high density and configurability. However, due to its high sensitivity to SEU, it is difficult to be applied in space. With the decrease of the feature sizes, SRAM-based FPGAs are more sensitive to SEU. Therefore, how to evaluate the sensitivity of a design to SEU in FPGA is very important for the application in space. This paper presents a fast fault injection platform for SRAM-based FPGA, which is able to emulate multiple SEUs in SRAM-based FPGA to evaluate the sensitivity of the design in FPGA and repair the accumulated SEUs by fault injection platform itself. Faults are injected through a configuration port ICAP inside the FPGA by modifying the data in the configuration memory. This paper uses the internal injection through ICAP which is faster than external injection. The locations injected are available at every clock in order to speed up. The fault injection module and the user design module are separated through a specific placement to avoid fault injection module injecting itself and leading to failure. We show the sensitivity of ISCAS85 benchmark circuits configured in PFGA and validate the fault injection platform by comparing the error rate and resource utilization.