Xuebing Cao

Impact of BTI aging effect on soft error rate of combination circuit

Aging and soft errors have become the two most critical reliability issues for nano-scale CMOS circuit. First, in this paper, the aging effect due to bias temperature instability (BTI) is analyzed on different logic gate using 45nm Technology, and simulated the critical charge and delay which can influence soft error rate (SER) result. Second, a method of SER calculation considering BTI effect is given. As a result, we find that the effect of PBTI on the circuit is less than that of NBTI on the critical charge. The critical charge and delay affect the masking effect and the probability of an error in SER calculation. Experimental result shows that the SER calculation considering BTI effect is feasible and the impact of BTI on benchmark circuits SER is up to 21.6%.

Design of Area-Efficient and Highly Reliable RHBD 10T Memory Cell for Aerospace Applications

In this brief, based on upset physical mechanism together with reasonable transistor size, a robust 10T memory cell is first proposed to enhance the reliability level in aerospace radiation environment, while keeping the main advantages of small area, low power, and high stability. Using Taiwan Semiconductor Manufacturing Company 65-nm CMOS commercial standard process, simulations performed in Cadence Spectre demonstrate the ability of the proposed radiation-hardened-by-design 10T cell to tolerate both <inline-formula> <tex-math notation=LaTeX>

A fast fault injection platform of multiple SEUs for SRAM-based FPGAs

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A 13T radiation-hardened memory cell for low-voltage operation and ultra-low power space applications

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Heavy ion-induced single event upset sensitivity evaluation of 3D integrated static random access memory

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A Fault Injection Platform Supporting Both SEU and Multiple SEUs for SRAM-Based FPGA

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A Layout-Based Soft Error Vulnerability Estimation Approach for Combinational Circuits Considering Single Event Multiple Transients (SEMTs)

In recent years, SRAM-based FPGAs have been applied in space due to its high density and configurability. However, due to its high sensitivity to SEU, it is difficult to be applied in space. With the decrease of the feature sizes, SRAM-based FPGAs are more sensitive to SEU. Therefore, how to evaluate the sensitivity of a design to SEU in FPGA is very important for the application in space. This paper presents a fast fault injection platform for SRAM-based FPGA, which is able to emulate multiple SEUs in SRAM-based FPGA to evaluate the sensitivity of the design in FPGA and repair the accumulated SEUs by fault injection platform itself. Faults are injected through a configuration port ICAP inside the FPGA by modifying the data in the configuration memory. This paper uses the internal injection through ICAP which is faster than external injection. The locations injected are available at every clock in order to speed up. The fault injection module and the user design module are separated through a specific placement to avoid fault injection module injecting itself and leading to failure. We show the sensitivity of ISCAS85 benchmark circuits configured in PFGA and validate the fault injection platform by comparing the error rate and resource utilization.

Soft error optimization of combinational circuit based on gate sizing and multi-objective particle swarm optimization algorithm

This paper presents a novel memory cell design as a variant of Lior Atias 13T cell (mentioned as LA13T cell in this paper) for low-voltage operation and ultra-low power space applications. Using C-element as a replacement of dual-driven inverters in the LA13T cell, our proposed radiation hardened by design memory cell (referred to as RHD13T) can effectively block the unwanted paths from Vdd to Gnd during SEU occurrence, while the problem will be appeared on LA13T cell. Simulation results show that, at the expense of an increased area for obtaining the same drive capability as LA13T cell at each internal store node, RHD13T cell shows better power consumption than LA13T cell during SET occurrence.