Mark Ingels

A 40 nm CMOS 0.4–6 GHz Receiver Resilient to Out-of-Band Blockers

A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.

Design strategies and decoupling techniques for reducing the effects of electrical interference in mixed-mode IC's

A key issue in the successful integration of analog circuits is a stable analog power supply. Traditional on-chip decoupling methods exhibit transients in the supply or voltage drops and power losses. This paper introduces the RLC decoupling method that features an enhanced transient response while being especially suited for low-power, low voltage applications. Both a theoretical and a practical approach are presented together with measurement results. As the benefits of a stable local power supply can be lost by the inadequate connection of two subcircuits with relative variations on the local grounds, a differential approach of signal transfer is proposed. Furthermore, the effect of a good local decoupling can be deteriorated by substrate noise, so some attention is given to this problem too.

A CMOS 18 THz/spl Omega/ 248 Mb/s transimpedance amplifier and 155 Mb/s LED-driver for low cost optical fiber links

The realization of a complete low cost CMOS optical fiber link using a LED and PIN as optical components is presented. The driver and receiver are realized in a standard 0.8 /spl mu/m digital CMOS process which makes integration with a DSP possible. The driver is a current steering transistor combined with a small quiescent current source. The modulation current is 60 mA which allows a 155 Mb/s optical data-rate. The receiver is a three-stage transimpedance amplifier followed by a signal converter which provides digital output signal levels. The three-stage configuration makes possible the realization of a high transimpedance (150 k/spl Omega/), necessary to obtain a high sensitivity, combined with a high bandwidth. The achieved optical data-rate is 240 Mb/s for 1 /spl mu/A input modulation currents. This results in a transimpedance bandwidth of 18 THz/spl Omega/, which is one order of magnitude higher than recently published circuits. The speed performance of the total link is limited by the optical time-constant of the LED, leading to a 155 Mb/s optical link, designed for use in four-fiber interboard connections in 622 Mb/s B-ISDN systems. >

A 2-mm

A software-defined radio (SDR) should theoretically receive any modulated frequency channel in the (un)licensed spectrum, and guarantee top performance with energy savings, while still being integrated in a digital CMOS technology. This paper demonstrates a practical 0.1-5 GHz front-end implementation for such an SDR concept, including receiver and local oscillator (LO), with only 2-mm2 core area occupation in a 45-nm CMOS process. This scalable radio uses shunt-shunt feedback LNAs, a passive mixer with enhanced out-of-band IIP3, and a fifth order low-area 0.5-20 MHz baseband filter. LO quadrature signals are generated from a dual-VCO 4-10 GHz fractional-N PLL. With noise figure between 2.3 dB and 6.5 dB, out-of-band IIP3 between -3 dBm and -10 dBm, and total power consumption between 59 and 115 mW from a 1.1-V supply voltage, the presented prototype favorably compares with state-of-the-art dedicated radios while enabling, for the first time, wideband reconfigurable performance and energy scalability.

^{2}

This paper presents a 1-Gb/s optical receiver with full rail-to-rail output swing realized in a standard 0.7-/spl mu/m CMOS technology. The receiver consists of a 1-k/spl Omega/ transimpedance preamplifier followed by a postamplifier based on a biased inverter chain. The latter performs both a linear and a limiting amplification. The automatic biasing of the chain is provided through an offset tolerant replica circuit. The receiver requires no external components or biasing voltages. It is designed for a relatively large 0.8-pF input capacitance and is fed from a single 5-V power supply. These properties make the circuit suitable for a commercial environment. A sensitivity of 10 /spl mu/A was measured at 1 Gb/s. The complete receiver, including all biasing and replicas, consumes approximately 100 mW from the 5-V supply. When powered from a 3.3-V supply, a maximal bit rate of 600 Mb/s is achieved, while the power consumption is reduced to approximately 26.5 mW.

0.1–5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

A 5 mm2 transceiver front-end suitable for a software-defined radio (SDR) platform is implemented in a 40-nm LP digital CMOS technology. Tailored for all modern communication standards relevant for a modern handheld mobile device (2G/3G/4G cellular, WLAN, Bluetooth, GPS, broadcasting, etc.), it uses radio architectures and circuits that ensure flexible performance at a minimal cost in area and power consumption. The receive section features four parallel LNAs to cover the frequency range from 100 MHz up to 6 GHz, a 25 % duty cycle passive mixer with IIP2 calibration, fifth-order baseband filtering up to 20 MHz, variable-gain amplification, and a 10-b 65 MS/s 34 fj/conv-step SAR ADC. It achieves NF down to 2.4 dB, more than 30-dB EVM and 50-dBm IIP2. In the transmit section, main emphasis is given to the out-of-band noise requirement that enables SAW-less operation in FDD systems: a flexible reconstruction filter is followed by a voltage-sampling mixer and a variable gain PPA. The TX chain achieves 3.2% EVM at 0-dBm output power, with CNR down to-156 dBc/Hz. For frequency synthesis, two dual-VCO 5.9-12.8 GHz fractional-N PLLs are implemented together with a chain of divide-by-2 circuits for quadrature generation.

A 1-Gb/s, 0.7-/spl mu/m CMOS optical receiver with full rail-to-rail output swing

SDRs come of age ([1,2]) and transcend beyond just acquiring the reconfigura-bility to replace any standard radio: they develop toward systems where a simplified antenna interface can be used, with most dedicated filtering removed. This requires a receiver accommodating much higher linearity and resilience against out-of-band interference than a standard radio, still achieving competitive sensitivity (especially in the absence of interference). Mixer-first front-ends with excellent linearity have been reported [3]. However, their NF (including 1/f in absence of the LNA gain) is not competitive, and they may suffer from large LO feedthrough to the antenna (LOFT). Moreover they lack receiver functionality such as gain and filtering, which cannot be simply added without compromising linearity. A receiver with mixer-at-the-antenna-based bandpass filter [4] similarly may suffer from LOFT and increased N F. This work presents a full software-defined receiver with 3dB NF that tolerates 0dBm blockers with acceptable blocker NF at maximum gain. It achieves +10dBm out-of-band (OB) IIP3 and >+70dBm IIP2. Such a receiver is to operate using no other than harmonic-rejection filtering.

A 5 mm

The trend in wireless communication where terminals give their users ubiquitous access to a multitude of services drives the development of Software-Defined Radio (SDR) in deeply scaled CMOS. This is enhanced with the advent of LTE, a standard that is inherently so flexible that an SDR is its most economical implementation. This work presents an answer to that need with the development of a complete transceiver with RF, baseband and data converter circuits in 40nm LP CMOS.

^{2}

This paper presents a new approach to reduce the out of band quantization noise of Direct Digital RF Modulators (DDRM). The DDRM is organized in a FIR-like configuration to filter the quantization noise in the RX band directly at RF. To demonstrate the principle, a 0.9 GHz FIR IQ DDRM has been integrated in 130 nm CMOS. The transmitter achieves more than 22 dB reduction in the quantization noise floor to reach −152 dBc/Hz@20 MHz with a 200 KHz baseband tone. The actual DDRM is capable of both amplitude and phase modulation by using a new four-phases IQ architecture. This results in a reduced power consumption and chip area. The transmitter consumes 94 mW from a 2.7 V supply and achieves an average output power of 9.5 dBm. Leakage into the adjacent channel and into the next one of −35 dB and −53 dB, respectively have been measured for a 10 MHz OFDM signal. It also achieves −27.2 dB EVM with a 64QAM input signal.

40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

A Software-Defined Radio (SDR) analog front-end is presented that provides extensive programmability of LO generator, LNA, mixers, baseband filters and PPA, supporting various wireless communication standards while guaranteeing a near-optimal power/performance trade-off at any time. The circuit is integrated in a 0.13 mum CMOS technology with 1.2 V supply voltage. This transceiver covers the frequency range from 100 MHz up to 6 GHz by exploiting a flexible zero-IF architecture. The receive path achieves a Noise Figure of 4.8 dB at 174 MHz and 6 dB at 2.4 GHz. For a WLAN OFDM 64 QAM output, the transmitter achieves an EVM better than -29 dB for -0.5 dBm output power at 2.4 GHz and -3.1 dBm output power at 4.9 GHz.