Marian Verhelst

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

A 2.4-GHz 20–40-MHz Channel WLAN Digital Outphasing Transmitter Utilizing a Delay-Based Wideband Phase Modulator in 32-nm CMOS

A digital outphasing transmitter is presented for 2.4-GHz WiFi. The transmitter consists of two delay-based phase modulators and a 26-dBm integrated switching class-D power amplifier. The delay-based phase modulator delays incoming LO edges with a resolution of 1.4 ps (8 bit) required to meet WiFi requirements. A phase MUX architecture is proposed to implement switching between phases once every LO period (2.4 GHz) without generating detrimental glitches at the output. Due to its open-loop nature, the proposed phase modulator is capable of delivering wide OFDM bandwidths up to 40 MHz. The paper analyzes the impact of impairments, e.g., delay mismatch within the delay cells and outphasing mismatches, as well as associated mitigation techniques. The transmitter has been implemented in a 32-nm digital CMOS process and delivers an OFDM average power of 20 dBm with an overall system efficiency of 18.6% when transmitting 54-Mb/s 64QAM signal. The fully digital design is expected to further improve in power dissipation and chip-area with further CMOS scaling.

A Reconfigurable, 130 nm CMOS 108 pJ/pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging

This paper presents a fully integrated flexible ultra-low power UWB impulse radio receiver, capable of cm-accurate ranging. Ultra-low-power consumption is achieved by employing the quadrature analog correlating receiver architecture, by exploiting the duty-cycled nature of the system, by operating in the sub-1 GHz band as well as by careful circuit design. Two pulse rates, 39.0625 Mpulses per second (Mpps) and 19.531 Mpps, and a wide range of processing gains (0-18 dB) are supported. Also, the acquisition algorithm and accuracy can be adapted at run time. This flexible implementation allows to dynamically trade power consumption for performance depending on the operating conditions and the application requirements. The receiver prototype was manufactured in 130 nm CMOS and the active circuit area measures 4.52 mm2. The IC contains a complete analog front-end, digital backend and implements the algorithms necessary for acquisition, synchronization, data reception and ranging. Consuming 4.2 mW when operating at 39.0625 Mpps, it achieves an energy efficiency of 108 pJ/pulse. A 1.3 Mb/s wireless link over more than 10 m in an office-like environment has been demonstrated under direct line-of-sight (LOS) conditions with a raw packet-error-rate (PER) less than 10% and cm-accurate ranging.

A reconfigurable, 0.13µm CMOS 110pJ/pulse, fully integrated IR-UWB receiver for communication and sub-cm ranging

Wireless sensor networks have recently attracted increased research interest. An important enabler is a specialized energy-efficient, scalable radio. Typically modest data rates (≪1Mb/s) over a short radio range (≪10m) with accurate indoor ranging to identify and locate sensing nodes, are required at an extremely low energy consumption. A high degree of flexibility is needed at a small energy overhead in order to tailor the power-performance trade-off for each application specifically and to adapt optimally to the operating conditions.

Architectures for low power ultra-wideband radio receivers in the 3.1-5GHz band for data rates < 10Mbps

This paper compares different receiver architectures for UWB radio communication in the 3.1-5GHz band, targeting data rates up to 10Mbps, in terms of their BER performance and power consumption. A receiver, in which some correlations are carried out in the analog domain seems to outperform a fully digital receiver, commonly suggested for baseband UWB. This paper proves that for equal processing gain requirements the partially analog receiver consumes 7 times less power per received bit than the fully digital one.

System design of an ultra-low power, low data rate, pulsed UWB receiver in the 0-960 MHz band

This paper describes a complete system architecture for an ultra-low power, pulsed UWB receiver in the 0-960 MHz band for low data rate communication (10 kbps) in sensor networks, together with its acquisition algorithms and performance evaluation. Power consumption of this receiver is decreased impressively in relation to common fully digital receivers by shifting the matched filter operation to the analog domain, by using efficient acquisition schemes and by introducing extreme parallelism in the baseband. The optimal trade-off between a low power design and a good performance gain is searched. Sub 10 mW active power and sub 10 /spl mu/W standby power are targeted, to achieve an average power consumption (analog + baseband) of 70 /spl mu/W for data rates of 10 kbps, while realizing a processing gain of almost 30 dB.

A 0.3–2.6 TOPS/W precision-scalable processor for real-time large-scale ConvNets

A low-power precision-scalable processor for ConvNets or convolutional neural networks (CNN) is implemented in a 40nm technology. Its 256 parallel processing units achieve a peak 102GOPS running at 204MHz. To minimize energy consumption while maintaining throughput, this works is the first to both exploit the sparsity of convolutions and to implement dynamic precision-scalability enabling supply- and energy scaling. The processor is fully C-programmable, consumes 25-288mW at 204 MHz and scales efficiency from 0.3-2.6 real TOPS/W. This system hereby outperforms the state-of-the-art up to 3.9× in energy efficiency.

A Power-Scalable Channel-Adaptive Wireless Receiver Based on Built-In Orthogonally Tunable LNA

Most of the traditional RF circuits are static or minimally tunable using some digital controllability. For example, high power, low power and shut down modes are available in some commercially available transceivers. If available, the tuning knobs affect different specifications in an interdependent manner, resulting in changing several specifications when only one needs to be tuned. This is not enough for power optimal operation of complete self-aware self-adaptive circuits and systems. Independent or orthogonal tunability of the important conflicting specifications using built-in tuning knobs allow optimal adaptation of the wire-less systems. In this paper we demonstrate the design and benefits of orthogonal tuning knobs using an inductorless LNA as a test vehicle. The design of an orthogonally tunable LNA is discussed that has a 14 dB Gain tuning range and 30 dB OIP3 tuning range as its power consumption goes down by 20×. Measurement results on this LNA validate the concept of orthogonal tunability. Use of this orthogonally tunable LNA within an adaptive wireless receiver framework shows power savings of 2× compared to a static system and an extra savings of 22% compared to a traditional nonorthogonal adaptive system.

Power Consumption Minimization for MIMO Systems — A Cognitive Radio Approach

This paper shows how cognitive radio (CR) can help to optimize system power consumption of multiple input multiple output (MIMO) communication systems. Leveraging results from information theory and capabilities of a CR (e.g., the awareness of the component capabilities and characteristics), a theoretical framework is developed to minimize the system power consumption of MIMO systems while still considering radiated power. This paper mathematically formulates the system power consumption minimization problem under a sum rate constraint for MIMO systems. The impact of channel correlation and partial channel state information at the transmitter is considered. Numerical algorithms are developed to solve the constrained optimization problem. The simulation results show that significant power savings (e.g., up to 75% for a 4 × 4 MIMO system with Class A power amplifiers) can be achieved compared to conventional power allocation schemes. The results also show that the more computationally efficient suboptimal heuristic algorithms can achieve power savings comparable to the exhaustive search algorithm.

Systematic Analysis of Interleaved Digital-to-Analog Converters

A generalized theoretical analysis of interleaved digital-to-analog converters (DACs) is presented to explain the cancellation of image replicas. A new RF-DAC architecture comprising N -parallel DACs and using both clock and hold interleaving structure is proposed. The architecture is analyzed using a general mathematical model that can be extended to other types of interleaved DACs. Additional benefits of the proposed architecture, including bandwidth and resolution enhancements, are investigated. The model is extended to analyze return-to-zero variants of this architecture with a variable hold time period. The effect of different path mismatches is further examined.