Chunxiang Zhu

Conjugated-polymer-functionalized graphene oxide: synthesis and nonvolatile rewritable memory effect.

[*] Prof. Y. Chen, X.-D. Zhuang, P.-P. Li, B. Zhang, J.-H. Zhu, Y.-X. Li Key Laboratory for Advanced Materials Institute of Applied Chemistry East China University of Science and Technology 130 Meilong Road, Shanghai 200237 (P. R. China) E-mail: chentangyu@yahoo.com Prof. E.-T. Kang, Dr. G. Liu, Prof. K.-G. Neoh Department of Chemical & Biomolecular Engineering National University of Singapore 10 Kent Ridge, 119260 (Singapore) E-mail: cheket@nus.edu.sg Prof. Dr. C.-X. Zhu Department of Electrical & Computer Engineering National University of Singapore 10 Kent Ridge, 119260 (Singapore)

N-type Schottky barrier source/drain MOSFET using ytterbium silicide

Ytterbium silicide, for the first time, was used to form the Schottky barrier source/drain (S/D) of N-channel MOSFETs. The device fabrication was performed at low temperature, which is highly preferred in the establishment of Schottky barrier S/D transistor (SSDT) technology, including the HfO/sub 2/ gate dielectric, and HaN/TaN metal gate. The YbSi/sub 2 - x/ silicided N-SSDT has demonstrated a very promising characteristic with a recorded high I/sub on//l/sub off/ ratio of /spl sim/10/sup 7/ and a steep subthreshold slope of 75 mV/dec, which is attributed to the lower electron barrier height and better film morphology of the YbSi/sub 2 - x//Si contact compared with other self-aligned rare earth metal-(Erbium, Terbium, Dysprosium) silicided Schottky junctions.

A novel ultrathin elevated channel low-temperature poly-Si TFT

A novel ultrathin elevated channel thin-film transistor (UT-ECTFT) made using low-temperature poly-Si is proposed. The structure has an ultrathin channel region (300 /spl Aring/) and a thick drain/source region. The thin channel is connected to the heavily doped drain/source through a lightly doped overlapped region. The lightly doped overlapped region provides an effective way to spread out the electric field at the drain, thereby reducing significantly the lateral electric field there at high drain bias. Thus, the UT-ECTFT exhibits excellent current saturation characteristics even at high bias (V/sub ds/=30 V, V/sub gs/=20 V). Moreover, the UT-ECTFT has more than two times increase in on-state current and 3.5 times reduction in off-state current compared to conventional thick channel TFTs.

Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate

Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 A and a leakage current of 5.02×10−5 A/cm2 at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (∼400 °C) used in the chemical-vapor deposition process.

A simple and efficient solar cell parameter extraction method from a single current-voltage curve

In this work, a simple and efficient method for the extraction of all the parameters of a solar cell from a single current-voltage (I-V) curve under the constant illumination level is proposed. With the help of the Lambert W function, the explicit analytic expression for I is obtained. By reducing the number of the parameters, the expression for I only depends on the ideality factor n, the series resistance Rs, and the shunt resistance Rsh. This analytic expression is directly used to fit the experimental data and extract the device parameters. This simple solar cell parameter extraction method can be directly applied for all kinds of solar cells whose I-V characteristics follow the single-diode model. The parameters of various solar devices including silicon solar cells, silicon solar modules, dye-sensitized solar cells, and organic solar cells with standalone, tandem, and multi-junction structures have been successfully extracted by using our proposed method.

Electrical Conductance Tuning and Bistable Switching in Poly(N-vinylcarbazole)−Carbon Nanotube Composite Films

By varying the carbon nanotube (CNT) content in poly(N-vinylcarbazole) (PVK) composite thin films, the electrical conductance behavior of an indium-tin oxide/PVK-CNT/aluminum (ITO/PVK-CNT/Al) sandwich structure can be tuned in a controlled manner. Distinctly different electrical conductance behaviors, such as (i) insulator behavior, (ii) bistable electrical conductance switching effects (write-once read-many-times (WORM) memory effect and rewritable memory effect), and (iii) conductor behavior, are discernible from the current density-voltage characteristics of the composite films. The turn-on voltage of the two bistable conductance switching devices decreases and the ON/OFF state current ratio of the WORM device increases with the increase in CNT content of the composite film. Both the WORM and rewritable devices are stable under a constant voltage stress or a continuous pulse voltage stress, with an ON/OFF state current ratio in excess of 10(3). The conductance switching effects of the composite films have been attributed to electron trapping in the CNTs of the electron-donating/hole-transporting PVK matrix.

A high-density MIM capacitor (13 fF/μm/sup 2/) using ALD HfO 2 dielectrics

Metal-insulator-metal (MIM) capacitors with different HfO/sub 2/ thickness have been investigated. The results show that both the capacitance density and voltage coefficients of capacitance (VCCs) increase with decreasing HfO/sub 2/ thickness. In addition, it is found that the VCCs decrease logarithmically with increasing thickness. Furthermore, the MIM capacitor with 10-nm HfO/sub 2/ shows a record high capacitance density of 13 fF//spl mu/m/sup 2/ and a VCC of 607 ppm/V, which can meet the requirement of the International Technology Roadmap for Semiconductors. It can also provide a low leakage current of 5.95 /spl times/ 10/sup -8/A/cm/sup 2/ at room temperature at 1 V, low tangent values below 0.05, and a small frequency dependence. These results indicate that the devices are suitable for use in silicon integrated circuit applications.

A high performance MIM capacitor using HfO 2 dielectrics

Metal-insulator-metal (MIM) capacitors with a 56 nm thick HfO/sub 2/ high-/spl kappa/ dielectric film have been fabricated and demonstrated for the first of time with a low thermal budget (/spl sim/200/spl deg/C). Voltage linearity, temperature coefficients of capacitance, and electrical properties are all characterized. The results show that the HfO/sub 2/ MIM capacitor can provide a higher capacitance density than Si/sub 3/N/sub 4/ MIM capacitor while still maintaining comparable voltage and temperature coefficients of capacitance. In addition, a low leakage current of 2/spl times/10/sup -9/ A/cm/sup 2/ at 3 V is achieved. All of these make the HfO/sub 2/ MIM capacitor to be very suitable for use in silicon RF and mixed signal IC applications.

Alternative surface passivation on germanium for metal-oxide-semiconductor applications with high-k gate dielectric

An alternative surface passivation process for high-k Ge metal-oxide-semiconductor (MOS) device has been studied. The surface SiH4 annealing was implemented prior to HfO2 deposition. X-ray photoelectron spectroscopy analysis results show that the SiH4 surface passivation can greatly prevent the formation of unstable germanium oxide at the surface and suppress the Ge out-diffusion after the HfO2 deposition. The electrical measurement shows that an equivalent oxide thickness of 13.5A and a leakage current of 1.16×10−5A∕cm2 at 1V gate bias was achieved for TaN∕HfO2∕Ge MOS capacitors with the SiH4 surface treatment.

A TaN-HfO/sub 2/-Ge pMOSFET with NovelSiH/sub 4/ surface passivation

In this letter, we demonstrate a novel surface passivation process for HfO/sub 2/ Ge pMOSFETs using SiH/sub 4/ surface annealing prior to HfO/sub 2/ deposition. By using SiH/sub 4/ passivation, a uniform amorphous interfacial layer is formed after device fabrication. Electrical results show that the HfO/sub 2/ Ge MOSFET with Si-passivation exhibits less frequency dispersion, narrower gate leakage current distribution, and a /spl sim/140% higher peak mobility than that of the device with surface nitridation.