Dim-Lee Kwong

Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof

Method of forming high pressure silicon oxynitride gate dielectrics

Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant

ULTRATHIN HIGH-K GATE DIELECTRIC WITH FAVORABLE INTERFACE PROPERTIES FOR IMPROVED SEMICONDUCTOR DEVICE PERFORMANCE

Method for achieving a highly reliable oxide film

Method of forming ultra thin gate dielectric for high performance semiconductor devices

CMOS transistor design for shared N+/P+ electrode with enhanced device performance

High K integration of gate dielectric with integrated spacer formation for high speed CMOS

Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants

Semiconductor topography employing a nitrogenated shallow trench isolation structure