Chunyuan Zhou

Injection-Locking-Based Power and Speed Optimization of CML Dividers

In this brief, a novel power and speed optimization methodology of current mode logic (CML) dividers is presented, which is based on the injection-locking concept from injection-locked frequency dividers. It helps to realize a CML divider of high performance, including high operation frequency, low power consumption, and a wide division locking range. This concept is newly introduced to explain why shunt peaking can help to improve speed. Following the proposed optimization methodology, a high-performance 20-GHz CML divider with an active inductor tank in 0.18-μm complementary metal-oxide-semiconductor is designed as an example. The measured results show that it achieves a FOMPdc of 23.3 dB with only 4.3 mW of power consumption, which provides the correctness of the proposed methodology in the design of high-performance CML dividers.

A 24-GHz fully integrated phase-locked loop for 60-GHz beamforming

A 24-GHz fully integrated integer-N phase-locked loop (PLL) is presented in this paper. Benefiting from the bias noise filtering technique, the voltage controlled oscillator (VCO) in the loop achieves a low phase noise. Moreover, the supply voltage of VCO is as low as 0.8-V due to the low-threshold-voltage transistors used in the design. The proposed PLL is fabricated in 90-nm CMOS technology. The measurement results show that the PLL achieves a phase noise of -85dBc/Hz in band and -112dBc/Hz at 10-MHz offset from the carrier frequency of 24GHz. The whole chip occupies an area of 1.3 × 0.8mm2 and consumes 36-mW from a 1.2-V supply voltage (a 0.8-V supply voltage for VCO) excluding output driving buffers.

A lumped Elements varactor-loaded Transmission-Line phase shifter at 60GHz

The design flow of a lumped Elements varactor-loaded Transmission-Line phase shifter (VLTL) is illustrated and a 60GHz phase shifter of this kind is implemented in IBM 90nm CMOS process in this paper. The proposed VLTL is area-saving, occupying only 937um × 110um as it uses inductors instead of long transmission lines. This phase shifter is digitally controlled and need no extra DACs to realize phase tuning range. It is an absolutely passive network and consumes nearly zero DC power. The simulation results verify that this phase shifter can achieve a 180° phase control range with a phase resolution of 22.1°, an insertion loss of 2.5 to 10.9dB. The return loss ȣS11ȣ,ȣS22ȣ are better than 16dB.

A transformer-based filtering technique to lower LC-oscillator phase noise

Phase noise of oscillators can be improved through noise filtering. This paper presents a transformer-based harmonic filtering technique to improve the phase noise performance of the fully differential CMOS LC oscillators. The primary and secondary of the transformer are placed at the sources of NMOS and PMOS differential pairs, respectively. Due to the extra degree of freedom introduced by the transformer, the filter can resonate at two different frequencies, which are designed to be the second and fourth harmonics. The analysis of the filtering method is presented and principles of operation are discussed in details. The performance is compared with other filtering techniques, and the simulation results show improved FoM compared to published literature.

A 50% duty cycle wide-locking range divide-by-3 divider up to 6GHz

A synchronous 50% duty cycle divide-by-3 divider up to 6GHz is presented in this paper. The proposed architecture is composed of three identical delay cells with active inductor tank, which are injected by 3 input current with 120° phase splitting. The input current is provided by a double-balanced mixer mixing the outputs of the delay cells with the input clock signal. These cells are not stand alone, but coupled with each other. Thanks to the coupling and input current with 120° phase splitting, the outputs of the three cells are locked at the 1/3 input frequencies with 60°phase splitting, which means that the outputs are of an accurate 50% duty cycle. Injection behavior model is proposed for analysis, and some design guidelines are acquired here. This divider is fabricated in 0.18µm CMOS process and works with a nominal supply voltage of 1.8V. The measured results indicate that the locking range of this divider is 4GHz (from 2.5GHz to 6.5GHz) at an input power of 0dBm with about 4mW power dissipation. As high as 28dB second harmonic suppression of a single-ended output proves that this proposed divider realizes a true 50% duty cycle signal.

A wide-locking range V-Band injection-locked frequency divider

A novel injection-locked frequency divider for V-Band frequency synthesis is proposed in this paper. Thanks to the nMOS realized in triple-well technology with N-well floating, the source and its body can be connected together to get rid of the body effect and thus reduce the nMOS threshold voltage, which helps enhance the injection efficiency in the direct injection-locked frequency dividers. The proposed divider is implemented in 90-nm CMOS technology and draws only 1-mA from 0.9-V low voltage supply. The simulation results show that the proposed frequency divider can work from 52-GHz to 65-GHz with 0-dBm input power. The division bandwidth is improved by 5-GHz comparing to the conventional structures.

A complementary injection technique for performance enhancing of CML dividers

A complementary injection technique is proposed to enhance the overall performance of current mode logic (CML) dividers in this paper. With injection currents introduced by pMOSFETs, the equivalent injection efficiency of CML dividers are improved and thus CML dividers achieve a better performance. Extensive simulation results show that the proposed technique improves the division bandwidth of 24-GHz divide-by-2 CML divider by 5GHz, which is from 12GHz to 30GHz. The designed divide-by-2 CML frequency divider draws only 2-mA current from 1.2-V supply.

A 24GHz low phase noise feedback CMOS LC-VCO

This paper proposes an effective method to improve phase noise in voltage controlled oscillator (VCO), which is realized with 90nm RF CMOS technology. A current source is used in this design to control the VCO power consumption, while the filtering technique is incorporated to reduce VCO phase noise, and a feedback loop from output to input is also adopted to further improve the phase noise performance. A •100.85 — •104.7dBc/Hz phase noise is achieved at 1MHz offset, and the frequency tuning range(FTR) spans from 24.7GHz to 28.8GHz, with a total power consumption of 5.5mW from 1.2V supply.